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20 | 20 | #include <zephyr/logging/log.h>
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21 | 21 | LOG_MODULE_REGISTER(clock_control);
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22 | 22 |
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| 23 | +#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP) |
| 24 | +#define AUD_PLL_DIV_CLK0_LPCG UINT_TO_POINTER(0x59D20000) |
| 25 | +static sc_ipc_t ipc_handle; |
| 26 | +#endif |
| 27 | + |
23 | 28 | #ifdef CONFIG_SPI_NXP_LPSPI
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24 | 29 | static const clock_name_t lpspi_clocks[] = {
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25 | 30 | kCLOCK_Usb1PllPfd1Clk,
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@@ -81,6 +86,15 @@ static const clock_ip_name_t sai_clocks[] = {
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81 | 86 | #endif
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82 | 87 | #endif /* CONFIG_DAI_NXP_SAI */
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83 | 88 |
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| 89 | +#ifdef CONFIG_DAI_NXP_ESAI |
| 90 | +#if defined(CONFIG_SOC_MIMX8QX6_ADSP) || defined(CONFIG_SOC_MIMX8QM6_ADSP) |
| 91 | +static const clock_ip_name_t esai_clocks[] = { |
| 92 | + kCLOCK_AUDIO_Esai0, |
| 93 | + kCLOCK_AUDIO_Esai1, |
| 94 | +}; |
| 95 | +#endif |
| 96 | +#endif /* CONFIG_DAI_NXP_ESAI */ |
| 97 | + |
84 | 98 | #if defined(CONFIG_I2C_NXP_II2C)
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85 | 99 | static const clock_ip_name_t i2c_clk_root[] = {
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86 | 100 | kCLOCK_RootI2c1,
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@@ -139,6 +153,27 @@ static int mcux_ccm_on(const struct device *dev,
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139 | 153 | #endif
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140 | 154 | #endif /* CONFIG_DAI_NXP_SAI */
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141 | 155 |
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| 156 | +#ifdef CONFIG_DAI_NXP_ESAI |
| 157 | +#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP) |
| 158 | + case IMX_CCM_ESAI0_CLK: |
| 159 | + case IMX_CCM_ESAI1_CLK: |
| 160 | + CLOCK_EnableClock(esai_clocks[instance]); |
| 161 | + return 0; |
| 162 | +#endif |
| 163 | +#endif /* CONFIG_DAI_NXP_ESAI */ |
| 164 | + |
| 165 | +#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP) |
| 166 | + case IMX_CCM_AUD_PLL_DIV_CLK0: |
| 167 | + /* ungate PLL parent */ |
| 168 | + sc_pm_clock_enable(ipc_handle, SC_R_AUDIO_PLL_0, |
| 169 | + SC_PM_CLK_MISC0, true, false); |
| 170 | + |
| 171 | + /* ungate the clock itself */ |
| 172 | + CLOCK_SetLpcgGate(AUD_PLL_DIV_CLK0_LPCG, true, false, 0xa); |
| 173 | + |
| 174 | + return 0; |
| 175 | +#endif |
| 176 | + |
142 | 177 | #if defined(CONFIG_ETH_NXP_ENET)
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143 | 178 | #ifdef CONFIG_SOC_SERIES_IMX8M
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144 | 179 | #define ENET_CLOCK kCLOCK_Enet1
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@@ -180,6 +215,27 @@ static int mcux_ccm_off(const struct device *dev,
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180 | 215 | return 0;
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181 | 216 | #endif
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182 | 217 | #endif /* CONFIG_DAI_NXP_SAI */
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| 218 | + |
| 219 | +#ifdef CONFIG_DAI_NXP_ESAI |
| 220 | +#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP) |
| 221 | + case IMX_CCM_ESAI0_CLK: |
| 222 | + case IMX_CCM_ESAI1_CLK: |
| 223 | + CLOCK_DisableClock(esai_clocks[instance]); |
| 224 | + return 0; |
| 225 | +#endif |
| 226 | +#endif /* CONFIG_DAI_NXP_ESAI */ |
| 227 | + |
| 228 | +#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP) |
| 229 | + case IMX_CCM_AUD_PLL_DIV_CLK0: |
| 230 | + /* gate the clock itself */ |
| 231 | + CLOCK_SetLpcgGate(AUD_PLL_DIV_CLK0_LPCG, false, false, 0xa); |
| 232 | + |
| 233 | + /* gate PLL parent */ |
| 234 | + sc_pm_clock_enable(ipc_handle, SC_R_AUDIO_PLL_0, |
| 235 | + SC_PM_CLK_MISC0, false, false); |
| 236 | + |
| 237 | + return 0; |
| 238 | +#endif |
183 | 239 | default:
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184 | 240 | (void)instance;
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185 | 241 | return 0;
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@@ -540,7 +596,6 @@ static DEVICE_API(clock_control, mcux_ccm_driver_api) = {
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540 | 596 | static int mcux_ccm_init(const struct device *dev)
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541 | 597 | {
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542 | 598 | #if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
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543 |
| - sc_ipc_t ipc_handle; |
544 | 599 | int ret;
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545 | 600 |
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546 | 601 | ret = sc_ipc_open(&ipc_handle, DT_REG_ADDR(DT_NODELABEL(scu_mu)));
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