drivers: dai: esai: add support for runtime PM

Add support for runtime PM.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

Author: LaurentiuM1234

drivers/dai/nxp/esai/esai.c

@@ -1,9 +1,12 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/pm/device_runtime.h>
+#include <zephyr/pm/device.h>
+
 #include "esai.h"
 
 /* TODO:
@@ -654,14 +657,12 @@ static const struct dai_properties
 
 static int esai_probe(const struct device *dev)
 {
-	/* nothing to be done here but mandatory to implement */
-	return 0;
+	return pm_device_runtime_get(dev);
 }
 
 static int esai_remove(const struct device *dev)
 {
-	/* nothing to be done here but mandatory to implement */
-	return 0;
+	return pm_device_runtime_put(dev);
 }
 
 static DEVICE_API(dai, esai_api) = {
@@ -673,6 +674,54 @@ static DEVICE_API(dai, esai_api) = {
 	.remove = esai_remove,
 };
 
+static int esai_clks_enable_disable(const struct device *dev, bool enable)
+{
+	const struct esai_config *cfg;
+	void *clk_id;
+	int i, ret;
+
+	cfg = dev->config;
+
+	for (i = 0; i < cfg->clk_data.clock_num; i++) {
+		clk_id = UINT_TO_POINTER(cfg->clk_data.clocks[i]);
+
+		if (enable) {
+			ret = clock_control_on(cfg->clk_data.dev, clk_id);
+		} else {
+			ret = clock_control_off(cfg->clk_data.dev, clk_id);
+		}
+
+		if (ret < 0) {
+			LOG_ERR("failed to gate/ungate clock %u: %d",
+				cfg->clk_data.clocks[i], ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+__maybe_unused static int esai_pm_action(const struct device *dev,
+					 enum pm_device_action action)
+{
+	bool enable = true;
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		enable = false;
+		break;
+	case PM_DEVICE_ACTION_TURN_ON:
+	case PM_DEVICE_ACTION_TURN_OFF:
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+
+	return esai_clks_enable_disable(dev, enable);
+}
+
 static int esai_init(const struct device *dev)
 {
 	const struct esai_config *cfg;
@@ -684,12 +733,19 @@ static int esai_init(const struct device *dev)
 
 	device_map(&data->regmap, cfg->regmap_phys, cfg->regmap_size, K_MEM_CACHE_NONE);
 
+#ifndef CONFIG_PM_DEVICE_RUNTIME
+	ret = esai_clks_enable_disable(dev, true);
+	if (ret < 0) {
+		return ret;
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
 	ret = esai_parse_pinmodes(cfg, data);
 	if (ret < 0) {
 		return ret;
 	}
 
-	return 0;
+	return pm_device_runtime_enable(dev);
 }
 
 #define ESAI_INIT(inst)							\
@@ -749,14 +805,17 @@ static struct esai_config esai_config_##inst = {			\
 	.pinmodes_size = ARRAY_SIZE(pinmodes_##inst),			\
 	.clock_cfg = clock_cfg_##inst,					\
 	.clock_cfg_size = ARRAY_SIZE(clock_cfg_##inst),			\
+	.clk_data = ESAI_CLOCK_DATA_DECLARE(inst),			\
 };									\
 									\
 static struct esai_data esai_data_##inst = {				\
 	.cfg.type = DAI_IMX_ESAI,					\
 	.cfg.dai_index = DT_INST_PROP_OR(inst, dai_index, 0),		\
 };									\
 									\
-DEVICE_DT_INST_DEFINE(inst, &esai_init, NULL,				\
+PM_DEVICE_DT_INST_DEFINE(inst, esai_pm_action);				\
+									\
+DEVICE_DT_INST_DEFINE(inst, &esai_init, PM_DEVICE_DT_INST_GET(inst),	\
 		      &esai_data_##inst, &esai_config_##inst,		\
 		      POST_KERNEL, CONFIG_DAI_INIT_PRIORITY,		\
 		      &esai_api);					\

drivers/dai/nxp/esai/esai.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include <zephyr/drivers/dai.h>
 #include <zephyr/device.h>
 #include <zephyr/dt-bindings/dai/esai.h>
+#include <zephyr/drivers/clock_control.h>
 
 #include <fsl_esai.h>
 
@@ -152,6 +153,34 @@ LOG_MODULE_REGISTER(nxp_dai_esai);
 #define ESAI_PIN_IS_USED(data, which)\
 	(((data)->pcrc & BIT(which)) && ((data->prrc) & BIT(which)))
 
+#define IDENTITY_VARGS(V, ...) IDENTITY(V)
+
+#define _ESAI_CLOCK_INDEX_ARRAY(inst)\
+	LISTIFY(DT_INST_PROP_LEN_OR(inst, clocks, 0), IDENTITY_VARGS, (,))
+
+#define _ESAI_GET_CLOCK_ID(clock_idx, inst)\
+	DT_INST_PHA_BY_IDX_OR(inst, clocks, clock_idx, name, 0x0)
+
+#define _ESAI_CLOCK_ID_ARRAY(inst)\
+	FOR_EACH_FIXED_ARG(_ESAI_GET_CLOCK_ID, (,), inst, _ESAI_CLOCK_INDEX_ARRAY(inst))
+
+#define _ESAI_GET_CLOCK_ARRAY(inst)						\
+	COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, nxp_dai_esai), clocks),	\
+		    ({ _ESAI_CLOCK_ID_ARRAY(inst) }),				\
+		    ({ }))
+
+#define _ESAI_GET_CLOCK_CONTROLLER(inst)					\
+	COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, nxp_dai_esai), clocks),	\
+		    (DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst))),			\
+		    (NULL))
+
+#define ESAI_CLOCK_DATA_DECLARE(inst)				\
+{								\
+	.clocks = (uint32_t [])_ESAI_GET_CLOCK_ARRAY(inst),	\
+	.clock_num = DT_INST_PROP_LEN_OR(inst, clocks, 0),	\
+	.dev = _ESAI_GET_CLOCK_CONTROLLER(inst),		\
+}
+
 struct esai_data {
 	mm_reg_t regmap;
 	struct dai_config cfg;
@@ -170,6 +199,12 @@ struct esai_data {
 	uint32_t pcrc;
 };
 
+struct esai_clock_data {
+	uint32_t clock_num;
+	uint32_t *clocks;
+	const struct device *dev;
+};
+
 struct esai_config {
 	uint32_t regmap_phys;
 	uint32_t regmap_size;
@@ -182,6 +217,7 @@ struct esai_config {
 	uint32_t pinmodes_size;
 	uint32_t *clock_cfg;
 	uint32_t clock_cfg_size;
+	struct esai_clock_data clk_data;
 };
 
 /* this needs to perfectly match SOF's struct sof_ipc_dai_esai_params */