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lib/stm32: update BLE stm32wba to cube version V1.6.0 #280

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Merged
merged 2 commits into from
May 20, 2025
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lib/stm32: update BLE stm32wba to cube version V1.6.0 #280

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ee8d1c2
lib/stm32: update BLE stm32wba to cube version V1.6.0
asm5878 May 15, 2025
698ae8c
lib/stm32: add STM32WBA6 BLE support
asm5878 May 16, 2025
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48 changes: 23 additions & 25 deletions lib/stm32wba/BLE_TransparentMode/Core/Inc/app_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -155,12 +155,13 @@
*
* When CFG_LPM_LEVEL is set to:
* - 0 : Low Power Mode is not activated, RUN mode will be used.
* - 1 : Low power active, the one selected with CFG_LPM_STDBY_SUPPORTED
* - 2 : In addition, force to disable modules to reach lowest power figures.
* - 1 : Low power active, mode selected with CFG_LPM_STDBY_SUPPORTED
* - 2 : In addition log and debug are disabled to reach lowest power figures.
*
* When CFG_LPM_STDBY_SUPPORTED is set to:
* - 2 : Stop mode 2 is used as low power mode (if supported by target)
* - 1 : Standby is used as low power mode.
* - 0 : Standby is not used, so stop mode 1 is used as low power mode.
* - 0 : Stop mode 1 is used as low power mode.
*
******************************************************************************/
#define CFG_LPM_LEVEL (1)
Expand Down Expand Up @@ -214,12 +215,10 @@ typedef enum
/**
* Enable or disable LOG over UART in the application.
* Low power level(CFG_LPM_LEVEL) above 1 will disable LOG.
* Standby low power mode(CFG_LPM_STDBY_SUPPORTED) will disable LOG.
* Standby low power mode(CFG_LPM_STDBY_SUPPORTED) above 0 will disable LOG.
*/
#define CFG_LOG_SUPPORTED (0U)

/* Usart used by LOG */

/* Configure Log display settings */
#define CFG_LOG_INSERT_COLOR_INSIDE_THE_TRACE (0U)
#define CFG_LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE (0U)
Expand All @@ -238,6 +237,18 @@ typedef enum

/******************************************************************************
* Configure Log level for Application
*
* APPLI_CONFIG_LOG_LEVEL can be any value of the Log_Verbose_Level_t enum.
*
* APPLI_CONFIG_LOG_REGION can either be :
* - LOG_REGION_ALL_REGIONS to enable all regions
* or
* - One or several specific regions (any value except LOG_REGION_ALL_REGIONS)
* from the Log_Region_t enum and matching the mask value.
*
* For example, to enable both LOG_REGION_BLE and LOG_REGION_APP,
* the value assigned to the define is :
* (1U << LOG_REGION_BLE | 1U << LOG_REGION_APP)
******************************************************************************/
#define APPLI_CONFIG_LOG_LEVEL LOG_VERBOSE_INFO
#define APPLI_CONFIG_LOG_REGION (LOG_REGION_ALL_REGIONS)
Expand Down Expand Up @@ -267,8 +278,8 @@ typedef enum
CFG_TASK_BLE_HOST,
CFG_TASK_AMM,
CFG_TASK_BPKA,
CFG_TASK_FLASH_MANAGER,
CFG_TASK_BLE_TIMER_BCKGND,
CFG_TASK_FLASH_MANAGER,
/* USER CODE BEGIN CFG_Task_Id_t */
TASK_BUTTON_1,
TASK_BUTTON_2,
Expand Down Expand Up @@ -364,26 +375,15 @@ typedef enum
/******************************************************************************
* HW RADIO configuration
******************************************************************************/
/* Do not modify - must be 1 */
#define USE_RADIO_LOW_ISR (1)

/* Do not modify - must be 1 */
#define NEXT_EVENT_SCHEDULING_FROM_ISR (1)

/* Link Layer uses temperature based calibration (0 --> NO ; 1 --> YES) */
#define USE_TEMPERATURE_BASED_RADIO_CALIBRATION (0)

#define RADIO_INTR_NUM RADIO_IRQn /* 2.4GHz RADIO global interrupt */
#define RADIO_INTR_PRIO_HIGH (0) /* 2.4GHz RADIO interrupt priority when radio is Active */
#define RADIO_INTR_PRIO_LOW (5) /* 2.4GHz RADIO interrupt priority when radio is Not Active - Sleep Timer Only */

#if (USE_RADIO_LOW_ISR == 1)
#define RADIO_SW_LOW_INTR_NUM HASH_IRQn /* Selected interrupt vector for 2.4GHz RADIO low ISR */
#define RADIO_SW_LOW_INTR_PRIO (14) /* 2.4GHz RADIO low ISR priority */
#endif /* USE_RADIO_LOW_ISR */

/* Link Layer supported number of antennas */
#define RADIO_NUM_OF_ANTENNAS (4)

#define RCC_INTR_PRIO (1) /* HSERDY and PLL1RDY */

Expand All @@ -397,12 +397,10 @@ typedef enum
#define CFG_EXTERNAL_PA_ENABLE (0)

#define CFG_BLE_AOA_AOD_ENABLE (0)
#define CFG_RADIO_NUM_OF_ANTENNAS (8) /* Link Layer supported number of antennas */

/* Custom LSE sleep clock accuracy to use if both conditions are met:
* - LSE is selected as Link Layer sleep clock source
* - the LSE used is different from the default one.
*/
#define CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE (0)
/* Radio sleep clock LSE accuracy configuration */
#define CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE (0x00)

/* USER CODE BEGIN Radio_Configuration */

Expand Down Expand Up @@ -472,12 +470,12 @@ typedef enum
#endif /* CFG_DEBUGGER_LEVEL */
#endif /* CFG_LPM_LEVEL */

#if (CFG_LPM_STDBY_SUPPORTED == 1)
#if (CFG_LPM_STDBY_SUPPORTED != 0) && (CFG_LPM_LEVEL != 0)
#if CFG_LOG_SUPPORTED
#undef CFG_LOG_SUPPORTED
#define CFG_LOG_SUPPORTED (0)
#endif /* CFG_LOG_SUPPORTED */
#endif /* CFG_LPM_STDBY_SUPPORTED */
#endif /* (CFG_LPM_STDBY_SUPPORTED > 0) && (CFG_LPM_LEVEL != 0) */

/* USER CODE BEGIN Defines_2 */

Expand Down
44 changes: 23 additions & 21 deletions lib/stm32wba/BLE_TransparentMode/STM32_WPAN/Target/linklayer_plat.c
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
*/
/* USER CODE END Header */

#ifndef __ZEPHYR__

#include "stm32wbaxx_hal.h"
#include "stm32wbaxx_hal_conf.h"
#include "stm32wbaxx_ll_rcc.h"
Expand All @@ -31,10 +31,12 @@
#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
#include "adc_ctrl.h"
#endif /* (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) */

#ifndef __ZEPHYR__
#if (CFG_LPM_LEVEL != 0)
#include "stm32_lpm.h"
#include "stm32_lpm_if.h"
#endif /* (CFG_LPM_LEVEL != 0) */

/* USER CODE BEGIN Includes */

/* USER CODE END Includes */
Expand Down Expand Up @@ -78,7 +80,6 @@ void LINKLAYER_PLAT_ClockInit(void)
/* Enable AHB5ENR peripheral clock (bus CLK) */
__HAL_RCC_RADIO_CLK_ENABLE();
}

#ifndef __ZEPHYR__
/**
* @brief Link Layer active waiting loop.
Expand All @@ -87,12 +88,12 @@ void LINKLAYER_PLAT_ClockInit(void)
*/
void LINKLAYER_PLAT_DelayUs(uint32_t delay)
{
__IO register uint32_t Delay = delay * (SystemCoreClock / 1000000U);
do
{
__NOP();
}
while (Delay --);
__IO register uint32_t Delay = delay * (SystemCoreClock / 1000000U);
do
{
__NOP();
}
while (Delay --);
}

/**
Expand All @@ -113,8 +114,12 @@ void LINKLAYER_PLAT_Assert(uint8_t condition)
*/
void LINKLAYER_PLAT_WaitHclkRdy(void)
{
/* Wait on radio bus clock readiness */
while(HAL_RCCEx_GetRadioBusClockReadiness() != RCC_RADIO_BUS_CLOCK_READY);
/* Wait on radio bus clock readiness if it has been turned of */
if (AHB5_SwitchedOff == 1)
{
AHB5_SwitchedOff = 0;
while (radio_sleep_timer_val == ll_intf_cmn_get_slptmr_value());
}
}

/**
Expand Down Expand Up @@ -470,16 +475,15 @@ void LINKLAYER_PLAT_StopRadioEvt(void)
*/
void LINKLAYER_PLAT_RCOStartClbr(void)
{
#if (CFG_SCM_SUPPORTED == 1)
#if (CFG_LPM_LEVEL != 0)
#if (CFG_LPM_STDBY_SUPPORTED == 1)
UTIL_LPM_SetOffMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_DISABLE);
#endif /* (CFG_LPM_STDBY_SUPPORTED == 1) */
PWR_DisableSleepMode();
/* Disabling stop mode prevents also from entering in standby */
UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_DISABLE);
#endif /* (CFG_LPM_LEVEL != 0) */
#if (CFG_SCM_SUPPORTED == 1)
scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_32MHZ);
while (LL_PWR_IsActiveFlag_VOS() == 0);
#endif /* CFG_SCM_SUPPORTED */
#endif /* (CFG_SCM_SUPPORTED == 1) */
}

/**
Expand All @@ -489,16 +493,14 @@ void LINKLAYER_PLAT_RCOStartClbr(void)
*/
void LINKLAYER_PLAT_RCOStopClbr(void)
{
#if (CFG_SCM_SUPPORTED == 1)
#if (CFG_LPM_LEVEL != 0)
#if (CFG_LPM_STDBY_SUPPORTED == 1)
UTIL_LPM_SetOffMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_ENABLE);
#endif /* (CFG_LPM_STDBY_SUPPORTED == 1) */
PWR_EnableSleepMode();
UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_ENABLE);
#endif /* (CFG_LPM_LEVEL != 0) */
#if (CFG_SCM_SUPPORTED == 1)
scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_16MHZ);
while (LL_PWR_IsActiveFlag_VOS() == 0);
#endif /* CFG_SCM_SUPPORTED */
#endif /* (CFG_SCM_SUPPORTED == 1) */
}

/**
Expand Down
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