s32: drivers: s32ze: psi5: patch for nocache section

Use zephyr .nocache section for non-cacheable variables.

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>

Author: congnguyenhuu

s32/drivers/s32ze/Psi5/src/Psi5_Ip.c

@@ -139,9 +139,9 @@ static const PSI5_MemMapPtr Psi5_Ip_axBaseAddresses[PSI5_INSTANCE_COUNT] = IP_PS
 #define PSI5_START_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE
 #include "Psi5_MemMap.h"
 
-static Psi5_Ip_ConfigType const *Psi5_Ip_pUsedConfig  = NULL_PTR;
-static Psi5_Ip_AvailableMessagesType Psi5_Ip_axMessages[PSI5_INSTANCE_COUNT][PSI5_CHANNEL_COUNT];
-static boolean Psi5_Ip_bDriverInitialized = FALSE;
+VAR_SEC_NOCACHE(Psi5_Ip_pUsedConfig) static Psi5_Ip_ConfigType const *Psi5_Ip_pUsedConfig  = NULL_PTR;
+VAR_SEC_NOCACHE(Psi5_Ip_axMessages) static Psi5_Ip_AvailableMessagesType Psi5_Ip_axMessages[PSI5_INSTANCE_COUNT][PSI5_CHANNEL_COUNT];
+VAR_SEC_NOCACHE(Psi5_Ip_bDriverInitialized) static boolean Psi5_Ip_bDriverInitialized = FALSE;
 
 #define PSI5_STOP_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE
 #include "Psi5_MemMap.h"

s32/drivers/s32ze/Rte/src/SchM_Psi5.c

@@ -99,18 +99,18 @@ extern "C"{
 ==================================================================================================*/
 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
 #include "Rte_MemMap.h"
-static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
-static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
-static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
-static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
-static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
-static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
-static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
-static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
-static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
-static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
-static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
-static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_00) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_01) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_02) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_03) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_04) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_05) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
+VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
 
 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
 #include "Rte_MemMap.h"