Pango-FPGA

Signal Generator, Oscilloscope, Logic Analyzer

Team DUB

👨‍🎓 😇Yuheng Su, Postgraduate in NJUEE.

👨‍🎓 😅Xuanji Wang, Postgraduate in NJUEE;

👨‍🎓 😋Zikang Wang, Postgraduate in NJUEE;

🟩IN 5 WE TRUST

File tree

📁sparrow_soc: comprehensive sparrow_soc soc project

📁dds: signal generator

📁dso: digital storage oscilloscope

📁la: logic analyzer

📁dso_lite: lite version dso(1024-fft supported)

📁slave_board: slave_board to implement 2-channel device

📁doc: documents

TODO list

1.RTL design ✅

2.SoC integration ✅

3.FPGA verification ✅

4.FPGA cascade ✅ (Ethernet/2-Channel DDS & DSO)