@@ -507,12 +507,12 @@ def get_inv(y, a):
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else :
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io_args .append (("o" , "D_IN_0" , i [bit ]))
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elif isinstance (buffer , io .FFBuffer ):
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- m .submodules += RequirePosedge (self .i_domain )
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+ m .submodules += RequirePosedge (buffer .i_domain )
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i_type = 0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
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io_args .append (("i" , "INPUT_CLK" , ClockSignal (buffer .i_domain )))
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io_args .append (("o" , "D_IN_0" , i [bit ]))
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elif isinstance (buffer , io .DDRBuffer ):
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- m .submodules += RequirePosedge (self .i_domain )
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+ m .submodules += RequirePosedge (buffer .i_domain )
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i_type = 0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
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io_args .append (("i" , "INPUT_CLK" , ClockSignal (buffer .i_domain )))
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io_args .append (("o" , "D_IN_0" , i0 [bit ]))
@@ -524,12 +524,12 @@ def get_inv(y, a):
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o_type = 0b1010 # PIN_OUTPUT_TRISTATE
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io_args .append (("i" , "D_OUT_0" , o [bit ]))
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elif isinstance (buffer , io .FFBuffer ):
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- m .submodules += RequirePosedge (self .o_domain )
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+ m .submodules += RequirePosedge (buffer .o_domain )
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o_type = 0b1101 # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
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io_args .append (("i" , "OUTPUT_CLK" , ClockSignal (buffer .o_domain )))
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io_args .append (("i" , "D_OUT_0" , o [bit ]))
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elif isinstance (buffer , io .DDRBuffer ):
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- m .submodules += RequirePosedge (self .o_domain )
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+ m .submodules += RequirePosedge (buffer .o_domain )
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o_type = 0b1100 # PIN_OUTPUT_DDR_ENABLE_REGISTERED
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io_args .append (("i" , "OUTPUT_CLK" , ClockSignal (buffer .o_domain )))
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io_args .append (("i" , "D_OUT_0" , o0 [bit ]))
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