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lines changed Original file line number Diff line number Diff line change @@ -330,8 +330,15 @@ def escape_one(match):
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return f"_{ ord (match .group (1 )[0 ]):02x} _"
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return "" .join (escape_one (m ) for m in re .finditer (r"([^A-Za-z0-9_])|(.)" , string ))
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- def tcl_quote (string ):
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- return '"' + re .sub (r"([$[\\])" , r"\\\1" , string ) + '"'
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+ def tcl_quote (string , quirk = None ):
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+ escaped = '"' + re .sub (r"([$[\\])" , r"\\\1" , string ) + '"'
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+ if quirk == "Diamond" :
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+ # Diamond seems to assign `clk\$2` as a name for the Verilog net `\clk$2 `, and
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+ # `clk\\\$2` as a name for the Verilog net `\clk\$2 `.
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+ return escaped .replace ("\\ " , "\\ \\ " )
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+ else :
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+ assert quirk is None
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+ return escaped
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def verbose (arg ):
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if get_override_flag ("verbose" ):
Original file line number Diff line number Diff line change @@ -686,9 +686,9 @@ class LatticePlatform(TemplatedPlatform):
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set_hierarchy_separator {/}
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{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
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{% if port_signal is not none -%}
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- create_clock -name {{port_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_quote}}]
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+ create_clock -name {{port_signal.name|tcl_quote("Diamond") }} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_quote("Diamond") }}]
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{% else -%}
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- create_clock -name {{net_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_quote}}]
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+ create_clock -name {{net_signal.name|tcl_quote("Diamond") }} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_quote("Diamond") }}]
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{% endif %}
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{% endfor %}
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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