vendor._lattice: reflow to 100 columns. NFC

Author: whitequark

amaranth/vendor/_lattice.py

@@ -543,7 +543,7 @@ class LatticePlatform(TemplatedPlatform):
 
     # Oxide templates
 
-    _oxide_required_tools = [ 
+    _oxide_required_tools = [
         "yosys",
         "nextpnr-nexus",
         "prjoxide"
@@ -579,7 +579,7 @@ class LatticePlatform(TemplatedPlatform):
         "{{name}}.pdc": r"""
             # {{autogenerated}}
             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
-                ldc_set_location -site {{ '{' }}{{pin_name}}{{ '}' }} {{'['}}get_ports {{port_name}}{{']'}} 
+                ldc_set_location -site {{ '{' }}{{pin_name}}{{ '}' }} {{'['}}get_ports {{port_name}}{{']'}}
                 {% if attrs -%}
                 ldc_set_port -iobuf {{ '{' }}{%- for key, value in attrs.items() %}{{key}}={{value}} {% endfor %}{{ '}' }} {{'['}}get_ports {{port_name}}{{']'}}
                 {% endif %}
@@ -605,7 +605,7 @@ class LatticePlatform(TemplatedPlatform):
         {{invoke_tool("nextpnr-nexus")}}
             {{get_override("nextpnr_opts")|options}}
             --log {{name}}.tim
-            --device {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}}            
+            --device {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}}
             --pdc {{name}}.pdc
             --json {{name}}.json
             --fasm {{name}}.fasm
@@ -818,7 +818,8 @@ def __init__(self, *, toolchain=None):
         device = self.device.lower()
         if device.startswith(("lfe5", "lae5")):
             self.family = "ecp5"
-        elif device.startswith(("lcmxo2-", "lcmxo3l", "lcmxo3d", "lamxo2-", "lamxo3l", "lamxo3d", "lfmnx-")):
+        elif device.startswith(("lcmxo2-", "lcmxo3l", "lcmxo3d", "lamxo2-", "lamxo3l", "lamxo3d",
+                                "lfmnx-")):
             self.family = "machxo2"
         elif device.startswith(("lifcl-", "lfcpnx-", "lfd2nx-", "lfmxo5-", "ut24c")):
             self.family = "nexus"
@@ -921,30 +922,36 @@ def create_missing_domain(self, name):
             m = Module()
             if self.default_clk == "OSCG":
                 if not hasattr(self, "oscg_div"):
-                    raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
-                                     "and 128")
+                    raise ValueError(
+                        "OSCG divider (oscg_div) must be an integer between 2 and 128")
                 if not isinstance(self.oscg_div, int) or self.oscg_div < 2 or self.oscg_div > 128:
-                    raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
-                                     "and 128, not {!r}"
-                                     .format(self.oscg_div))
+                    raise ValueError(
+                        f"OSCG divider (oscg_div) must be an integer between 2 and 128, "
+                        f"not {self.oscg_div!r}")
                 clk_i = Signal()
                 m.submodules += Instance("OSCG", p_DIV=self.oscg_div, o_OSC=clk_i)
             elif self.default_clk == "OSCH":
                 osch_freq = self.osch_frequency
                 if osch_freq not in self._supported_osch_freqs:
-                    raise ValueError("Frequency {!r} is not valid for OSCH clock. Valid frequencies are {!r}"
-                             .format(osch_freq, self._supported_osch_freqs))
+                    raise ValueError(
+                        f"Frequency {osch_freq!r} is not valid for OSCH clock. "
+                        f"Valid frequencies are {self._supported_osch_freqs!r}")
                 osch_freq_param = f"{float(osch_freq):.2f}"
                 clk_i = Signal()
-                m.submodules += Instance("OSCH", p_NOM_FREQ=osch_freq_param, i_STDBY=Const(0), o_OSC=clk_i, o_SEDSTDBY=Signal())
+                m.submodules += Instance("OSCH",
+                    p_NOM_FREQ=osch_freq_param,
+                    i_STDBY=Const(0),
+                    o_OSC=clk_i,
+                    o_SEDSTDBY=Signal()
+                )
             elif self.default_clk == "OSCA":
                 if not hasattr(self, "osca_div"):
-                    raise ValueError("OSCA divider (osca_div) must be an integer between 2 "
-                                      "and 256")
+                    raise ValueError(
+                        f"OSCA divider (osca_div) must be an integer between 2 and 256")
                 if not isinstance(self.osca_div, int) or self.osca_div < 2 or self.osca_div > 256:
-                    raise ValueError("OSCA divider (osca_div) must be an integer between 2 "
-                                     "and 256, not {!r}"
-                                     .format(self.osca_div))
+                    raise ValueError(
+                        f"OSCA divider (osca_div) must be an integer between 2 and 256, "
+                        f"not {self.osca_div!r}")
                 clk_i = Signal()
                 m.submodules += Instance("OSCA",
                     p_HF_CLK_DIV=str(self.osca_div - 1),
@@ -968,17 +975,15 @@ def create_missing_domain(self, name):
                 # Here we build a simple reset synchronizer from D-type FFs with a positive-level
                 # asynchronous preset which we tie low
                 m.submodules += [
-                    Instance(
-                        "FD1P3BX",
+                    Instance("FD1P3BX",
                         p_GSR="DISABLED",
                         i_CK=clk_i,
                         i_D=~rst_i,
                         i_SP=Const(1),
                         i_PD=Const(0),
                         o_Q=gsr0,
                     ),
-                    Instance(
-                        "FD1P3BX",
+                    Instance("FD1P3BX",
                         p_GSR="DISABLED",
                         i_CK=clk_i,
                         i_D=gsr0,
@@ -992,9 +997,9 @@ def create_missing_domain(self, name):
                 m.submodules += [
                     Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
                     Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0,   o_Q=gsr1),
-                    # Although we already synchronize the reset input to user clock, SGSR has dedicated
-                    # clock routing to the center of the FPGA; use that just in case it turns out to be
-                    # more reliable. (None of this is documented.)
+                    # Although we already synchronize the reset input to user clock, SGSR has
+                    # dedicated clock routing to the center of the FPGA; use that just in case it
+                    # turns out to be more reliable. (None of this is documented.)
                     Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
                 ]
             # GSR implicitly connects to every appropriate storage element. As such, the sync