GitHub - wasifijaz/Digital-System-Design-Verilog-Implementation: Digital System Design Verilog Implementation

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
AND_2x1.v		AND_2x1.v
AND_2x1_tb.v		AND_2x1_tb.v
CLA_16bits.v		CLA_16bits.v
CLA_16bits_tb.v		CLA_16bits_tb.v
CLA_4bits_tb.v		CLA_4bits_tb.v
CLS_4bits.v		CLS_4bits.v
CSA16ins.v		CSA16ins.v
CSA16ins_tb.v		CSA16ins_tb.v
CSA4ins.v		CSA4ins.v
CSA4ins_tb.v		CSA4ins_tb.v
CSA8ins.v		CSA8ins.v
CSA8ins_tb.v		CSA8ins_tb.v
FA.v		FA.v
FA_tb.v		FA_tb.v
FIFO_Simple.v		FIFO_Simple.v
FIFO_Simple_tb.v		FIFO_Simple_tb.v
HA.v		HA.v
HA_4bits.v		HA_4bits.v
HA_4bits_tb.v		HA_4bits_tb.v
HA_tb.v		HA_tb.v
Incrementer.v		Incrementer.v
Incrementer_tb.v		Incrementer_tb.v
LIFO.v		LIFO.v
LIFO_FIFO.v		LIFO_FIFO.v
LIFO_Simple.v		LIFO_Simple.v
LIFO_Simple_tb.v		LIFO_Simple_tb.v
LIFO_tb.v		LIFO_tb.v
Lab6Task3.v		Lab6Task3.v
Lab6Task3_tb.v		Lab6Task3_tb.v
MUX4in.v		MUX4in.v
MUX4in_tb.v		MUX4in_tb.v
MUX_2x1.v		MUX_2x1.v
MUX_2x1_tb.v		MUX_2x1_tb.v
MUX_4in.v		MUX_4in.v
MUX_4in_tb.v		MUX_4in_tb.v
MUX_4x1.v		MUX_4x1.v
MUX_4x1_tb.v		MUX_4x1_tb.v
MUX_8x1.v		MUX_8x1.v
MUX_8x1_tb.v		MUX_8x1_tb.v
Mux2inLogical.v		Mux2inLogical.v
Mux2inLogical_tb.v		Mux2inLogical_tb.v
Mux4inLogical.v		Mux4inLogical.v
Mux4inLogical_tb.v		Mux4inLogical_tb.v
NAND_2x1.v		NAND_2x1.v
NAND_2x1_tb.v		NAND_2x1_tb.v
NOR_2x1.v		NOR_2x1.v
NOR_2x1_tb.v		NOR_2x1_tb.v
NOT_1x1.v		NOT_1x1.v
NOT_1x1_tb.v		NOT_1x1_tb.v
OR_2x1.v		OR_2x1.v
OR_2x1_tb.v		OR_2x1_tb.v
RCA_2stagepl.v		RCA_2stagepl.v
RCA_2stagepl_tb.v		RCA_2stagepl_tb.v
RCA_4bits.v		RCA_4bits.v
RCA_4bits_tb.v		RCA_4bits_tb.v
RCA_4stagepl.v		RCA_4stagepl.v
RCA_4stagepl_tb.v		RCA_4stagepl_tb.v
RCA_8bits.v		RCA_8bits.v
RCA_8bits_tb.v		RCA_8bits_tb.v
T4L4.v		T4L4.v
T4L4_tb.v		T4L4_tb.v
TASK2.v		TASK2.v
TASK2_tb.v		TASK2_tb.v
Task.v		Task.v
Task1.v		Task1.v
Task1_tb.v		Task1_tb.v
Task2.v		Task2.v
Task2_tb.v		Task2_tb.v
TaskTest.v		TaskTest.v
XNOR_2x1.v		XNOR_2x1.v
XNOR_2x1_tb.v		XNOR_2x1_tb.v
XOR_2x1.v		XOR_2x1.v
XOR_2x1_tb.v		XOR_2x1_tb.v
compliment2.v		compliment2.v
compliment2_tb.v		compliment2_tb.v
mod4.v		mod4.v
mod4_tb.v		mod4_tb.v
pow2.v		pow2.v
pow2_tb.v		pow2_tb.v
split_combine.v		split_combine.v
split_combine_tb.v		split_combine_tb.v
task.v		task.v
task1.v		task1.v
task1_tb.v		task1_tb.v
task2.v		task2.v
task2_tb.v		task2_tb.v
task3.v		task3.v
task3_tb.v		task3_tb.v
task5.v		task5.v
task5_tb.v		task5_tb.v

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