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154 Open 537 Closed
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Issues list

Assertion failed: *** FAILED *** (exit code = 5)when run-binary-debug file.riscv bug
#2244 opened Apr 22, 2025 by cinder023
3 tasks done
Mismatch in CoSpike co-simulation about CSR registers bug
#2243 opened Apr 22, 2025 by ZhongYic00
3 tasks done
chipyard 1.13 "riscv-isa-sim” build error! bug
#2241 opened Apr 21, 2025 by zzulb
3 tasks done
1
Encoutered kernel bug when running spec2017 bug
#2239 opened Apr 17, 2025 by AliciaAndries
3 tasks done
The segmentation fault is encountered when running the RTL simulation bug
#2238 opened Apr 17, 2025 by zhangkanqi
3 tasks done
1
encountering soft lockup when boot linux on 32+ cores FPGA design bug
#2236 opened Apr 14, 2025 by Charles-Tang
3 tasks done
1
Using Chipyard's default configuration ReRoCCManyGemminiConfig, the ReRoCC build failed. bug
#2235 opened Apr 14, 2025 by silencerains
3 tasks done
3
Project for Adding Custom ROCC Accelerator Instructions enhancement
#2227 opened Apr 2, 2025 by gongtengxinyi123
2 tasks done
Caliptra AES Arbiter bug
#2208 opened Mar 10, 2025 by AndyKim519
Chisel 7 Support enhancement
#2205 opened Mar 6, 2025 by tymcauley
2 tasks done
3
hartid in chipletConfig bug
#2204 opened Mar 4, 2025 by mohammadnouripoor
3 tasks done
Question about Transmitting an executable binary to FPGA via Serial port enhancement
#2151 opened Dec 12, 2024 by yueca
2 tasks done
1
basic design fail to meet timing and a really slow booting linux on VCU118 bug
#2119 opened Nov 8, 2024 by Charles-Tang
3 tasks done
7
How to configure asynchronous reset enhancement
#2098 opened Oct 25, 2024 by AD738560581
2 tasks done
5
Error: Failed to make rmapats.so bug
#2091 opened Oct 21, 2024 by RockyQLuo
3 tasks done
2
Numpy-1.26.4-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl is not a supported wheel on this platform bug
#2080 opened Oct 12, 2024 by ZechenM
3 tasks done
FireSim doesn't work with cloned configs + CloneLazyModule caveats bug
#2076 opened Oct 8, 2024 by abejgonzalez
3 tasks done
1
firesim debug：using config (Rocket chip+custom Axi4 Peripheral) on fpga, segmentation faullt occurs when accessing Specific peripheral address bug
#2062 opened Sep 26, 2024 by huchensong
3 tasks done
Sky130 + openroad documentation doesn't work bug
#2059 opened Sep 23, 2024 by arunlee77
3 tasks done
The current default IOBinder for Debug Module does not punch out the ndreset (and hartResetReq)? bug
#2048 opened Sep 15, 2024 by DecodeTheEncoded
3 tasks done
4
How to export my custom IO signals at RocketTile module to DigitalTop's IO? enhancement
#2046 opened Sep 14, 2024 by csgxiong
2 tasks done
2
Error while executing "make buildfile CONFIG=GemminiRocketConfig tutorial=sky130-openroad" bug
#2035 opened Sep 7, 2024 by chihyu-box
3 tasks done
2
How to Add a prefix at every module name when generating system verilog? enhancement
#2033 opened Sep 6, 2024 by csgxiong
2 tasks done
1
VLSI Flow broken for OpenRoad+Sky130 on chipyard 1.11.0 or above? bug
#2017 opened Aug 26, 2024 by Jerry-Tianchen
3 tasks done
Verilator simulations can be made an order of magnitude faster enhancement
#2000 opened Aug 13, 2024 by mayyxeng
2 tasks done
3
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