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table-size-reduction

Here are 3 public repositories matching this topic...

ollycassidy13 / ReducedLUT

A tool for compression of lookup tables and generation of their hardware files in Verilog for RTL designs

compression fpga neural-network rtl verilog hardware-acceleration lookup-table ip-generation rtl-generation table-size-reduction hardware-ip

Updated Mar 30, 2025
C++

kiabuzz / CompressedLUT

A tool to generate optimized hardware files for univariate functions.

hls rtl hardware-acceleration lookup-table lossless-compression ip-generation function-evaluation table-size-reduction table-based-function-implementation function-implementation hardware-ip

Updated Apr 5, 2024
C++

ollycassidy13 / CompressedLUT

A tool to generate optimized hardware files for univariate functions.

fpga rtl hardware-acceleration lookup-table lossless-compression function-evaluation table-size-reduction table-based-function-implementation function-implementation

Updated Sep 5, 2024
C++

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