A High-performance Timing Analysis Tool for VLSI Systems

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

5 Day TCL begginer to advanced training workshop by VSD

Incremental k-Critical Path Generation

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

TCL Script automating the frontend of ASIC design

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

CAD in NYCU

TCL Script to automate the generation of Pre-layout QoR results

Vending Machine Design using Verilog HDL built and tested in Vivado Design Suite

This repo implements VLSI static timing analysis using C++.

Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite

Executed the complete physical design flow of a 1x3 router, encompassing synthesis, floorplanning, placement, clock tree synthesis, routing, and static timing analysis using Synopsys Fusion Compiler on a 32nm technology node.

This project is the script for STA report violated path checks temporarily (not final version due to confidentiality).

This project is a part of the report for my 7th semester program elective (EC-4143 VLSI-CAD).

Rust bindings for OpenSTA