Skip to content
#

hierachical

Here are 11 public repositories matching this topic...

Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).

  • Updated Oct 31, 2025
  • Python

Improve this page

Add a description, image, and links to the hierachical topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the hierachical topic, visit your repo's landing page and select "manage topics."

Learn more