This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Binary adder implementation in the Game of Life written in JavaScript using canvas.

Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.

A simulation where I can connect virtual logic gates and build virtual CIs.

A Java binary calculator based on a system of gates

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

A 4bit Multiplier in VHDL

Digital System Design Lab Codes using Verilog

Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/

VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design

All the various adders in Verilog!

This repository contains HWs and material from the nand to tetris course

Different adders code in VHDL and Comparison

Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module

A repository for some modules I made while learning Verilog

CSE-2112 Digital Syatem Design LAb

bitwise operation examples

Assignment 3, Digital Logic Design Lab, Spring 2021, IIT Bombay

A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz

A Java program that converts a binary number into it's two's complement equivalent. This is used within the SimpleBinaryCalculator repository.