Simmerv is a RISC-V SoC emulator written in Rust and compilable to WebAssembly. It started as a fork of Takahiro's riscv-rust emulator, but by now 98% of the code has been rewritten, making it far more complete and faster. Ultimately, we expect it to become substantially faster, but this work is delayed until we are able to run standard benchmarks and off-the-shelf Linux distributions.
You can run Linux on the emulator in your browser: online demo is here
- Emulates RISC-V RV64GC_Zba_Zicond processor and peripheral devices (PLIC, CLINT, virtio block device and a UART)
- Targets native and WASM
- RV64IMAC
- RV64FD (PARTIALLY flags/rounding modes very lacking)
- RV64Zifencei
- RV64Zicsr
- Svnapot
- Zba (part of "B", RVA22)
- Zbb (part of "B", RVA22)
- Zbs (part of "B", RVA22)
- Zicond
- CSR (nearly complete)
- Sv39, Sv48, Sv57
- Privileged instructions
- [-] PMP (this is intensionally not implemented as it will negatively affect performance)
The emulator supports all instructions listed above but some (like many FP instructions) are not 100% to the spec.
- Boots Buildroot and Debian Trixie
- Linux OpenSBI and legacy BBL boot support
- Newer Linux kernel have issues (which is a problem for newer binaries)
- U-boot loads but hangs before hand-off; might be an issue with ELF loading
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Amortized decoding and instruction fusion via a instruction translation cache <<
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Snapshot and resume
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Disk support without an in-memory copy (can WASM support this?)
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Improve the disassembler to recognize pseudo ops like li, mv, ret, etc. (This requires a structural change).
$ cargo b -r --all
$ target/release/simmerv_cli linux/fw_payload.elf -f linux/rootfs.img$ ./run-riscv-tests.shSee wasm/web
See wasm/npm