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A fork of V2.2 of i2c_bus_master by Scott Larson of EEWIKI
https://www.digikey.com/eewiki/pages/viewpage.action?pageId=10125324
All credit to the original author.

I re-wrote the code to add flexability to handle the I2C devices I wanted to interface as well as allowing
the code to work with another project, VHDL Modular Blocks Examples to follow....

An incomplete list of changes:

• Changed std_logic_unsigned to std_logic_arith
• Change bus width to match bus master and allow longer transfers
• Made transfer length a parameter (nbits)
• Added a debug port
• Renamed state names to make more readable, added more states
• Added metastability latches for asynchronous inputs (ena)
• Add continue and repeated start as inputs to cover more use cases
• use to_X01 for SCL and SDA to make idle states easier to find in waveforms (with external 'H' pullup)
• Made SCL and SDA synchronous outputs rather than combinatorial

Portability

• Changed clk'event to falling_edge()
• Clk event method in VHDL is not a good idea for STD_LOGIC as there are more than 0-1 state changes
• e.g. H-1 would cause a clock.

Readability

• changed divider * 4 - 1 to (divider * 4) - 1 (implicit, possibly non portable, precedence)
• Changed case statement to if statement as the case is superfluous
• Over use of brackets in syntax, if ( x = y ) then becomes if x = y than

BUGS:

Had to remove the clock stretching feature, SCL_ENA removed to deal with physical devices that do not play ball (will restore with work round later)