Skip to content

Commit efe779a

Browse files
kaz7kaz7
authored
Merge pull request #152 from sx-aurora-dev/merge/ve-packed-fpbinops
Merge/ve packed fpbinops
2 parents 89ac75e + ef56ed6 commit efe779a

File tree

4 files changed

+172
-5
lines changed

4 files changed

+172
-5
lines changed

‎llvm/lib/Target/VE/VVPInstrPatternsVec.td

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -636,11 +636,16 @@ defm : Binary_vr_vv<vvp_shl, i64, v512i32, v512i1, "PVSLL">;
636636
// Floating-point arithmetic (512 elements)
637637
defm : Unary<vvp_frcp, i64, v512f32, v512i1, "PVRCP">;
638638

639-
defm : Binary_rv_vv<c_vvp_fadd, i64, v512f32, v512i1, "PVFADD">;
640-
defm : Binary_rv_vv<c_vvp_fmul, i64, v512f32, v512i1, "PVFMUL">;
641-
defm : Binary_rv_vv<vvp_fsub, i64, v512f32, v512i1, "PVFSUB">;
642-
defm : Binary_rv_vv<c_vvp_fminnum, i64, v512f32, v512i1, "PVFMIN">;
643-
defm : Binary_rv_vv<c_vvp_fmaxnum, i64, v512f32, v512i1, "PVFMAX">;
639+
defm : Binary_rv_vv<c_vvp_fadd,
640+
i64, v512f32, v512i1, "PVFADD">;
641+
defm : Binary_rv_vv<c_vvp_fmul,
642+
i64, v512f32, v512i1, "PVFMUL">;
643+
defm : Binary_rv_vv<vvp_fsub,
644+
i64, v512f32, v512i1, "PVFSUB">;
645+
defm : Binary_rv_vv<c_vvp_fminnum,
646+
i64, v512f32, v512i1, "PVFMIN">;
647+
defm : Binary_rv_vv<c_vvp_fmaxnum,
648+
i64, v512f32, v512i1, "PVFMAX">;
644649

645650
defm : Ternary<c_vvp_ffma, i64, v512f32, v512i1, "PVFMAD">;
646651
defm : Ternary<c_vvp_ffms, i64, v512f32, v512i1, "PVFMSB">;

‎llvm/test/CodeGen/VE/Packed/vp_fadd.ll

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <512 x float> @llvm.vp.fadd.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
5+
6+
define fastcc <512 x float> @test_vp_fadd_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_fadd_v512f32_vv:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
10+
; CHECK-NEXT: and %s0, %s0, (32)0
11+
; CHECK-NEXT: srl %s0, %s0, 1
12+
; CHECK-NEXT: lvl %s0
13+
; CHECK-NEXT: pvfadd %v0, %v0, %v1
14+
; CHECK-NEXT: b.l.t (, %s10)
15+
%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
16+
ret <512 x float> %r0
17+
}
18+
19+
define fastcc <512 x float> @test_vp_fadd_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_fadd_v512f32_rv:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s2, %s0, (32)1
23+
; CHECK-NEXT: srl %s0, %s0, 32
24+
; CHECK-NEXT: or %s0, %s0, %s2
25+
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
26+
; CHECK-NEXT: and %s1, %s1, (32)0
27+
; CHECK-NEXT: srl %s1, %s1, 1
28+
; CHECK-NEXT: lvl %s1
29+
; CHECK-NEXT: pvfadd %v0, %s0, %v0
30+
; CHECK-NEXT: b.l.t (, %s10)
31+
%xins = insertelement <512 x float> undef, float %s0, i32 0
32+
%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
33+
%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
34+
ret <512 x float> %r0
35+
}
36+
37+
define fastcc <512 x float> @test_vp_fadd_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
38+
; CHECK-LABEL: test_vp_fadd_v512f32_vr:
39+
; CHECK: # %bb.0:
40+
; CHECK-NEXT: and %s2, %s0, (32)1
41+
; CHECK-NEXT: srl %s0, %s0, 32
42+
; CHECK-NEXT: or %s0, %s0, %s2
43+
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
44+
; CHECK-NEXT: and %s1, %s1, (32)0
45+
; CHECK-NEXT: srl %s1, %s1, 1
46+
; CHECK-NEXT: lvl %s1
47+
; CHECK-NEXT: pvfadd %v0, %s0, %v0
48+
; CHECK-NEXT: b.l.t (, %s10)
49+
%yins = insertelement <512 x float> undef, float %s1, i32 0
50+
%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
51+
%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
52+
ret <512 x float> %r0
53+
}

‎llvm/test/CodeGen/VE/Packed/vp_fmul.ll

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <512 x float> @llvm.vp.fmul.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
5+
6+
define fastcc <512 x float> @test_vp_fmul_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_fmul_v512f32_vv:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
10+
; CHECK-NEXT: and %s0, %s0, (32)0
11+
; CHECK-NEXT: srl %s0, %s0, 1
12+
; CHECK-NEXT: lvl %s0
13+
; CHECK-NEXT: pvfmul %v0, %v0, %v1
14+
; CHECK-NEXT: b.l.t (, %s10)
15+
%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
16+
ret <512 x float> %r0
17+
}
18+
19+
define fastcc <512 x float> @test_vp_fmul_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_fmul_v512f32_rv:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s2, %s0, (32)1
23+
; CHECK-NEXT: srl %s0, %s0, 32
24+
; CHECK-NEXT: or %s0, %s0, %s2
25+
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
26+
; CHECK-NEXT: and %s1, %s1, (32)0
27+
; CHECK-NEXT: srl %s1, %s1, 1
28+
; CHECK-NEXT: lvl %s1
29+
; CHECK-NEXT: pvfmul %v0, %s0, %v0
30+
; CHECK-NEXT: b.l.t (, %s10)
31+
%xins = insertelement <512 x float> undef, float %s0, i32 0
32+
%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
33+
%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
34+
ret <512 x float> %r0
35+
}
36+
37+
define fastcc <512 x float> @test_vp_fmul_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
38+
; CHECK-LABEL: test_vp_fmul_v512f32_vr:
39+
; CHECK: # %bb.0:
40+
; CHECK-NEXT: and %s2, %s0, (32)1
41+
; CHECK-NEXT: srl %s0, %s0, 32
42+
; CHECK-NEXT: or %s0, %s0, %s2
43+
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
44+
; CHECK-NEXT: and %s1, %s1, (32)0
45+
; CHECK-NEXT: srl %s1, %s1, 1
46+
; CHECK-NEXT: lvl %s1
47+
; CHECK-NEXT: pvfmul %v0, %s0, %v0
48+
; CHECK-NEXT: b.l.t (, %s10)
49+
%yins = insertelement <512 x float> undef, float %s1, i32 0
50+
%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
51+
%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
52+
ret <512 x float> %r0
53+
}

‎llvm/test/CodeGen/VE/Packed/vp_fsub.ll

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <512 x float> @llvm.vp.fsub.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
5+
6+
define fastcc <512 x float> @test_vp_fsub_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_fsub_v512f32_vv:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
10+
; CHECK-NEXT: and %s0, %s0, (32)0
11+
; CHECK-NEXT: srl %s0, %s0, 1
12+
; CHECK-NEXT: lvl %s0
13+
; CHECK-NEXT: pvfsub %v0, %v0, %v1
14+
; CHECK-NEXT: b.l.t (, %s10)
15+
%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
16+
ret <512 x float> %r0
17+
}
18+
19+
define fastcc <512 x float> @test_vp_fsub_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
20+
; CHECK-LABEL: test_vp_fsub_v512f32_rv:
21+
; CHECK: # %bb.0:
22+
; CHECK-NEXT: and %s2, %s0, (32)1
23+
; CHECK-NEXT: srl %s0, %s0, 32
24+
; CHECK-NEXT: or %s0, %s0, %s2
25+
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
26+
; CHECK-NEXT: and %s1, %s1, (32)0
27+
; CHECK-NEXT: srl %s1, %s1, 1
28+
; CHECK-NEXT: lvl %s1
29+
; CHECK-NEXT: pvfsub %v0, %s0, %v0
30+
; CHECK-NEXT: b.l.t (, %s10)
31+
%xins = insertelement <512 x float> undef, float %s0, i32 0
32+
%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
33+
%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
34+
ret <512 x float> %r0
35+
}
36+
37+
define fastcc <512 x float> @test_vp_fsub_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
38+
; CHECK-LABEL: test_vp_fsub_v512f32_vr:
39+
; CHECK: # %bb.0:
40+
; CHECK-NEXT: and %s2, %s0, (32)1
41+
; CHECK-NEXT: srl %s0, %s0, 32
42+
; CHECK-NEXT: or %s0, %s0, %s2
43+
; CHECK-NEXT: lea %s2, 256
44+
; CHECK-NEXT: lvl %s2
45+
; CHECK-NEXT: vbrd %v1, %s0
46+
; CHECK-NEXT: adds.w.sx %s0, 1, %s1
47+
; CHECK-NEXT: and %s0, %s0, (32)0
48+
; CHECK-NEXT: srl %s0, %s0, 1
49+
; CHECK-NEXT: lvl %s0
50+
; CHECK-NEXT: pvfsub %v0, %v0, %v1
51+
; CHECK-NEXT: b.l.t (, %s10)
52+
%yins = insertelement <512 x float> undef, float %s1, i32 0
53+
%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
54+
%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
55+
ret <512 x float> %r0
56+
}

0 commit comments

Comments
 (0)