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Merge pull request #151 from sx-aurora-dev/feature/merge-upstream-20220202
Feature/merge upstream 20220202
2 parents daad16a + a539697 commit 89ac75e

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8 files changed

+148
-75
lines changed

8 files changed

+148
-75
lines changed

‎flang/lib/Optimizer/CodeGen/TypeConverter.h

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -111,11 +111,15 @@ class LLVMTypeConverter : public mlir::LLVMTypeConverter {
111111
});
112112
addConversion([&](mlir::TupleType tuple) {
113113
LLVM_DEBUG(llvm::dbgs() << "type convert: " << tuple << '\n');
114-
llvm::SmallVector<mlir::Type> inMembers;
115-
tuple.getFlattenedTypes(inMembers);
116114
llvm::SmallVector<mlir::Type> members;
117-
for (auto mem : inMembers)
118-
members.push_back(convertType(mem).cast<mlir::Type>());
115+
for (auto mem : tuple.getTypes()) {
116+
// Prevent fir.box from degenerating to a pointer to a descriptor in the
117+
// context of a tuple type.
118+
if (auto box = mem.dyn_cast<fir::BoxType>())
119+
members.push_back(convertBoxTypeAsStruct(box));
120+
else
121+
members.push_back(convertType(mem).cast<mlir::Type>());
122+
}
119123
return mlir::LLVM::LLVMStructType::getLiteral(&getContext(), members,
120124
/*isPacked=*/false);
121125
});
@@ -140,7 +144,12 @@ class LLVMTypeConverter : public mlir::LLVMTypeConverter {
140144
}
141145
llvm::SmallVector<mlir::Type> members;
142146
for (auto mem : derived.getTypeList()) {
143-
members.push_back(convertType(mem.second).cast<mlir::Type>());
147+
// Prevent fir.box from degenerating to a pointer to a descriptor in the
148+
// context of a record type.
149+
if (auto box = mem.second.dyn_cast<fir::BoxType>())
150+
members.push_back(convertBoxTypeAsStruct(box));
151+
else
152+
members.push_back(convertType(mem.second).cast<mlir::Type>());
144153
}
145154
if (mlir::failed(st.setBody(members, /*isPacked=*/false)))
146155
return failure();
@@ -227,6 +236,14 @@ class LLVMTypeConverter : public mlir::LLVMTypeConverter {
227236
/*isPacked=*/false));
228237
}
229238

239+
/// Convert fir.box type to the corresponding llvm struct type instead of a
240+
/// pointer to this struct type.
241+
mlir::Type convertBoxTypeAsStruct(BoxType box) {
242+
return convertBoxType(box)
243+
.cast<mlir::LLVM::LLVMPointerType>()
244+
.getElementType();
245+
}
246+
230247
unsigned characterBitsize(fir::CharacterType charTy) {
231248
return kindMapping.getCharacterBitsize(charTy.getFKind());
232249
}

‎flang/lib/Optimizer/Dialect/FIRType.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -61,11 +61,11 @@ static bool isaIntegerType(mlir::Type ty) {
6161
}
6262

6363
bool verifyRecordMemberType(mlir::Type ty) {
64-
return !(ty.isa<BoxType>() || ty.isa<BoxCharType>() ||
65-
ty.isa<BoxProcType>() || ty.isa<ShapeType>() ||
66-
ty.isa<ShapeShiftType>() || ty.isa<ShiftType>() ||
67-
ty.isa<SliceType>() || ty.isa<FieldType>() || ty.isa<LenType>() ||
68-
ty.isa<ReferenceType>() || ty.isa<TypeDescType>());
64+
return !(ty.isa<BoxCharType>() || ty.isa<BoxProcType>() ||
65+
ty.isa<ShapeType>() || ty.isa<ShapeShiftType>() ||
66+
ty.isa<ShiftType>() || ty.isa<SliceType>() || ty.isa<FieldType>() ||
67+
ty.isa<LenType>() || ty.isa<ReferenceType>() ||
68+
ty.isa<TypeDescType>());
6969
}
7070

7171
bool verifySameLists(llvm::ArrayRef<RecordType::TypePair> a1,

‎flang/test/Fir/types-to-llvm.fir

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -400,3 +400,21 @@ func private @foo2(%arg : !fir.tdesc<f32>)
400400
func private @foo3(%arg : !fir.tdesc<!fir.type<derived7{f1:f32,f2:f32}>>)
401401
// CHECK-LABEL: foo3
402402
// CHECK-SAME: !llvm.ptr<i8>
403+
404+
// -----
405+
406+
// Test nested tuple types
407+
func private @foo0(%arg0: tuple<i64, tuple<f32, i64>>)
408+
// CHECK-LABEL: foo0
409+
// CHECK-SAME: !llvm.struct<(i64, struct<(f32, i64)>)>
410+
411+
// -----
412+
413+
// Test that fir.box inside tuple and derived type are lowered to struct type.
414+
func private @foo0(%arg0: tuple<i64, !fir.box<i32>>)
415+
// CHECK-LABEL: foo0
416+
// CHECK-SAME: !llvm.struct<(i64, struct<(ptr<i32>, i{{.*}})>)>
417+
418+
func private @foo1(%arg0: !fir.type<derived8{a:i64,b:!fir.box<i32>}>)
419+
// CHECK-LABEL: foo1
420+
// CHECK-SAME: !llvm.struct<"derived8", (i64, struct<(ptr<i32>, i{{.*}})>)>

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 39 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -324,50 +324,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
324324
if (useSVEForFixedLengthVectorVT(VT))
325325
addRegisterClass(VT, &AArch64::ZPRRegClass);
326326
}
327-
328-
for (auto VT : { MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64 }) {
329-
setOperationAction(ISD::SADDSAT, VT, Legal);
330-
setOperationAction(ISD::UADDSAT, VT, Legal);
331-
setOperationAction(ISD::SSUBSAT, VT, Legal);
332-
setOperationAction(ISD::USUBSAT, VT, Legal);
333-
setOperationAction(ISD::UREM, VT, Expand);
334-
setOperationAction(ISD::SREM, VT, Expand);
335-
setOperationAction(ISD::SDIVREM, VT, Expand);
336-
setOperationAction(ISD::UDIVREM, VT, Expand);
337-
}
338-
339-
for (auto VT :
340-
{ MVT::nxv2i8, MVT::nxv2i16, MVT::nxv2i32, MVT::nxv2i64, MVT::nxv4i8,
341-
MVT::nxv4i16, MVT::nxv4i32, MVT::nxv8i8, MVT::nxv8i16 })
342-
setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Legal);
343-
344-
for (auto VT :
345-
{ MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32, MVT::nxv4f32,
346-
MVT::nxv2f64 }) {
347-
setCondCodeAction(ISD::SETO, VT, Expand);
348-
setCondCodeAction(ISD::SETOLT, VT, Expand);
349-
setCondCodeAction(ISD::SETLT, VT, Expand);
350-
setCondCodeAction(ISD::SETOLE, VT, Expand);
351-
setCondCodeAction(ISD::SETLE, VT, Expand);
352-
setCondCodeAction(ISD::SETULT, VT, Expand);
353-
setCondCodeAction(ISD::SETULE, VT, Expand);
354-
setCondCodeAction(ISD::SETUGE, VT, Expand);
355-
setCondCodeAction(ISD::SETUGT, VT, Expand);
356-
setCondCodeAction(ISD::SETUEQ, VT, Expand);
357-
setCondCodeAction(ISD::SETUNE, VT, Expand);
358-
359-
setOperationAction(ISD::FREM, VT, Expand);
360-
setOperationAction(ISD::FPOW, VT, Expand);
361-
setOperationAction(ISD::FPOWI, VT, Expand);
362-
setOperationAction(ISD::FCOS, VT, Expand);
363-
setOperationAction(ISD::FSIN, VT, Expand);
364-
setOperationAction(ISD::FSINCOS, VT, Expand);
365-
setOperationAction(ISD::FEXP, VT, Expand);
366-
setOperationAction(ISD::FEXP2, VT, Expand);
367-
setOperationAction(ISD::FLOG, VT, Expand);
368-
setOperationAction(ISD::FLOG2, VT, Expand);
369-
setOperationAction(ISD::FLOG10, VT, Expand);
370-
}
371327
}
372328

373329
// Compute derived properties from the register classes
@@ -1163,9 +1119,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
11631119
}
11641120
}
11651121

1166-
if (Subtarget->hasSVE())
1167-
setOperationAction(ISD::VSCALE, MVT::i32, Custom);
1168-
11691122
setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom);
11701123

11711124
setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Custom);
@@ -1224,6 +1177,15 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
12241177
setOperationAction(ISD::SELECT_CC, VT, Expand);
12251178
setOperationAction(ISD::ROTL, VT, Expand);
12261179
setOperationAction(ISD::ROTR, VT, Expand);
1180+
1181+
setOperationAction(ISD::SADDSAT, VT, Legal);
1182+
setOperationAction(ISD::UADDSAT, VT, Legal);
1183+
setOperationAction(ISD::SSUBSAT, VT, Legal);
1184+
setOperationAction(ISD::USUBSAT, VT, Legal);
1185+
setOperationAction(ISD::UREM, VT, Expand);
1186+
setOperationAction(ISD::SREM, VT, Expand);
1187+
setOperationAction(ISD::SDIVREM, VT, Expand);
1188+
setOperationAction(ISD::UDIVREM, VT, Expand);
12271189
}
12281190

12291191
// Illegal unpacked integer vector types.
@@ -1237,6 +1199,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
12371199
MVT::nxv2f16, MVT::nxv4f16, MVT::nxv2f32})
12381200
setOperationAction(ISD::BITCAST, VT, Custom);
12391201

1202+
for (auto VT :
1203+
{ MVT::nxv2i8, MVT::nxv2i16, MVT::nxv2i32, MVT::nxv2i64, MVT::nxv4i8,
1204+
MVT::nxv4i16, MVT::nxv4i32, MVT::nxv8i8, MVT::nxv8i16 })
1205+
setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Legal);
1206+
12401207
for (auto VT : {MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1}) {
12411208
setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
12421209
setOperationAction(ISD::SELECT, VT, Custom);
@@ -1326,6 +1293,29 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
13261293
setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);
13271294

13281295
setOperationAction(ISD::SELECT_CC, VT, Expand);
1296+
setOperationAction(ISD::FREM, VT, Expand);
1297+
setOperationAction(ISD::FPOW, VT, Expand);
1298+
setOperationAction(ISD::FPOWI, VT, Expand);
1299+
setOperationAction(ISD::FCOS, VT, Expand);
1300+
setOperationAction(ISD::FSIN, VT, Expand);
1301+
setOperationAction(ISD::FSINCOS, VT, Expand);
1302+
setOperationAction(ISD::FEXP, VT, Expand);
1303+
setOperationAction(ISD::FEXP2, VT, Expand);
1304+
setOperationAction(ISD::FLOG, VT, Expand);
1305+
setOperationAction(ISD::FLOG2, VT, Expand);
1306+
setOperationAction(ISD::FLOG10, VT, Expand);
1307+
1308+
setCondCodeAction(ISD::SETO, VT, Expand);
1309+
setCondCodeAction(ISD::SETOLT, VT, Expand);
1310+
setCondCodeAction(ISD::SETLT, VT, Expand);
1311+
setCondCodeAction(ISD::SETOLE, VT, Expand);
1312+
setCondCodeAction(ISD::SETLE, VT, Expand);
1313+
setCondCodeAction(ISD::SETULT, VT, Expand);
1314+
setCondCodeAction(ISD::SETULE, VT, Expand);
1315+
setCondCodeAction(ISD::SETUGE, VT, Expand);
1316+
setCondCodeAction(ISD::SETUGT, VT, Expand);
1317+
setCondCodeAction(ISD::SETUEQ, VT, Expand);
1318+
setCondCodeAction(ISD::SETUNE, VT, Expand);
13291319
}
13301320

13311321
for (auto VT : {MVT::nxv2bf16, MVT::nxv4bf16, MVT::nxv8bf16}) {
@@ -1426,6 +1416,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
14261416
setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv4i1, MVT::nxv4i32);
14271417
setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv8i1, MVT::nxv8i16);
14281418
setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv16i1, MVT::nxv16i8);
1419+
1420+
setOperationAction(ISD::VSCALE, MVT::i32, Custom);
14291421
}
14301422

14311423
if (Subtarget->hasMOPS() && Subtarget->hasMTE()) {

‎llvm/test/Transforms/ArgumentPromotion/volatile-atomic.ll

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2+
; RUN: opt -S -argpromotion < %s | FileCheck %s
3+
4+
; Make sure volatile and atomic loads are not promoted.
5+
6+
define internal i32 @callee_volatile(i32* %p) {
7+
; CHECK-LABEL: @callee_volatile(
8+
; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* [[P:%.*]], align 4
9+
; CHECK-NEXT: ret i32 [[V]]
10+
;
11+
%v = load volatile i32, i32* %p
12+
ret i32 %v
13+
}
14+
15+
define void @caller_volatile(i32* %p) {
16+
; CHECK-LABEL: @caller_volatile(
17+
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @callee_volatile(i32* [[P:%.*]])
18+
; CHECK-NEXT: ret void
19+
;
20+
call i32 @callee_volatile(i32* %p)
21+
ret void
22+
}
23+
24+
define internal i32 @callee_atomic(i32* %p) {
25+
; CHECK-LABEL: @callee_atomic(
26+
; CHECK-NEXT: [[V:%.*]] = load atomic i32, i32* [[P:%.*]] seq_cst, align 4
27+
; CHECK-NEXT: ret i32 [[V]]
28+
;
29+
%v = load atomic i32, i32* %p seq_cst, align 4
30+
ret i32 %v
31+
}
32+
33+
define void @caller_atomic(i32* %p) {
34+
; CHECK-LABEL: @caller_atomic(
35+
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @callee_atomic(i32* [[P:%.*]])
36+
; CHECK-NEXT: ret void
37+
;
38+
call i32 @callee_atomic(i32* %p)
39+
ret void
40+
}

‎llvm/tools/llvm-reduce/DeltaManager.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,12 @@
3737

3838
using namespace llvm;
3939

40+
extern cl::OptionCategory LLVMReduceOptions;
4041
static cl::opt<std::string>
4142
DeltaPasses("delta-passes",
4243
cl::desc("Delta passes to run, separated by commas. By "
43-
"default, run all delta passes."));
44+
"default, run all delta passes."),
45+
cl::cat(LLVMReduceOptions));
4446

4547
#define DELTA_PASSES \
4648
DELTA_PASS("special-globals", reduceSpecialGlobalsDeltaPass) \

‎llvm/tools/llvm-reduce/deltas/Delta.cpp

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,25 +26,29 @@
2626

2727
using namespace llvm;
2828

29+
extern cl::OptionCategory LLVMReduceOptions;
30+
2931
static cl::opt<bool> AbortOnInvalidReduction(
3032
"abort-on-invalid-reduction",
31-
cl::desc("Abort if any reduction results in invalid IR"));
33+
cl::desc("Abort if any reduction results in invalid IR"),
34+
cl::cat(LLVMReduceOptions));
3235

3336
static cl::opt<unsigned int> StartingGranularityLevel(
3437
"starting-granularity-level",
35-
cl::desc("Number of times to divide chunks prior to first test"));
38+
cl::desc("Number of times to divide chunks prior to first test"),
39+
cl::cat(LLVMReduceOptions));
3640

3741
static cl::opt<bool> TmpFilesAsBitcode(
3842
"write-tmp-files-as-bitcode",
3943
cl::desc("Write temporary files as bitcode, instead of textual IR"),
40-
cl::init(false));
44+
cl::init(false), cl::cat(LLVMReduceOptions));
4145

4246
#ifdef LLVM_ENABLE_THREADS
4347
static cl::opt<unsigned> NumJobs(
4448
"j",
4549
cl::desc("Maximum number of threads to use to process chunks. Set to 1 to "
4650
"disables parallelism."),
47-
cl::init(1));
51+
cl::init(1), cl::cat(LLVMReduceOptions));
4852
#else
4953
unsigned NumJobs = 1;
5054
#endif

‎llvm/tools/llvm-reduce/llvm-reduce.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -36,44 +36,44 @@
3636

3737
using namespace llvm;
3838

39-
static cl::OptionCategory Options("llvm-reduce options");
39+
cl::OptionCategory LLVMReduceOptions("llvm-reduce options");
4040

4141
static cl::opt<bool> Help("h", cl::desc("Alias for -help"), cl::Hidden,
42-
cl::cat(Options));
42+
cl::cat(LLVMReduceOptions));
4343
static cl::opt<bool> Version("v", cl::desc("Alias for -version"), cl::Hidden,
44-
cl::cat(Options));
44+
cl::cat(LLVMReduceOptions));
4545

4646
static cl::opt<bool>
4747
PrintDeltaPasses("print-delta-passes",
4848
cl::desc("Print list of delta passes, passable to "
4949
"--delta-passes as a comma separated list"),
50-
cl::cat(Options));
50+
cl::cat(LLVMReduceOptions));
5151

5252
static cl::opt<std::string> InputFilename(cl::Positional, cl::Required,
5353
cl::desc("<input llvm ll/bc file>"),
54-
cl::cat(Options));
54+
cl::cat(LLVMReduceOptions));
5555

5656
static cl::opt<std::string>
5757
TestFilename("test", cl::Required,
5858
cl::desc("Name of the interesting-ness test to be run"),
59-
cl::cat(Options));
59+
cl::cat(LLVMReduceOptions));
6060

6161
static cl::list<std::string>
6262
TestArguments("test-arg", cl::ZeroOrMore,
6363
cl::desc("Arguments passed onto the interesting-ness test"),
64-
cl::cat(Options));
64+
cl::cat(LLVMReduceOptions));
6565

6666
static cl::opt<std::string> OutputFilename(
6767
"output", cl::desc("Specify the output file. default: reduced.ll|mir"));
6868
static cl::alias OutputFileAlias("o", cl::desc("Alias for -output"),
6969
cl::aliasopt(OutputFilename),
70-
cl::cat(Options));
70+
cl::cat(LLVMReduceOptions));
7171

7272
static cl::opt<bool>
7373
ReplaceInput("in-place",
7474
cl::desc("WARNING: This option will replace your input file "
7575
"with the reduced version!"),
76-
cl::cat(Options));
76+
cl::cat(LLVMReduceOptions));
7777

7878
enum class InputLanguages { None, IR, MIR };
7979

@@ -83,17 +83,17 @@ static cl::opt<InputLanguages>
8383
cl::init(InputLanguages::None),
8484
cl::values(clEnumValN(InputLanguages::IR, "ir", ""),
8585
clEnumValN(InputLanguages::MIR, "mir", "")),
86-
cl::cat(Options));
86+
cl::cat(LLVMReduceOptions));
8787

8888
static cl::opt<std::string> TargetTriple("mtriple",
8989
cl::desc("Set the target triple"),
90-
cl::cat(Options));
90+
cl::cat(LLVMReduceOptions));
9191

9292
static cl::opt<int>
9393
MaxPassIterations("max-pass-iterations",
9494
cl::desc("Maximum number of times to run the full set "
9595
"of delta passes (default=1)"),
96-
cl::init(1), cl::cat(Options));
96+
cl::init(1), cl::cat(LLVMReduceOptions));
9797

9898
static codegen::RegisterCodeGenFlags CGF;
9999

@@ -135,7 +135,7 @@ static std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
135135
int main(int Argc, char **Argv) {
136136
InitLLVM X(Argc, Argv);
137137

138-
cl::HideUnrelatedOptions({&Options, &getColorCategory()});
138+
cl::HideUnrelatedOptions({&LLVMReduceOptions, &getColorCategory()});
139139
cl::ParseCommandLineOptions(Argc, Argv, "LLVM automatic testcase reducer.\n");
140140

141141
bool ReduceModeMIR = false;

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