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[AMDGPU][GlobalISel] Add more sign/zero/any-extension tests
Add s1 to s16 cases, and for sgprs s1 to s64 and s32 to s64.
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir

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@@ -129,6 +129,26 @@ body: |
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---
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name: anyext_sgpr_s1_to_sgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s16
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
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; GCN-NEXT: $sgpr0 = COPY [[S_BFE_U32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s16) = G_ANYEXT %1
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%3:sgpr(s32) = G_ZEXT %2
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$sgpr0 = COPY %3
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...
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---
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name: anyext_sgpr_s1_to_sgpr_s32
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legalized: true
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regBankSelected: true
@@ -147,6 +167,46 @@ body: |
147167

148168
---
149169

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name: anyext_sgpr_s1_to_sgpr_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s64) = G_ANYEXT %1
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$sgpr0_sgpr1 = COPY %2
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...
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---
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name: anyext_vgpr_s1_to_vgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s16
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
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; GCN-NEXT: $vgpr0 = COPY [[V_BFE_U32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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%2:vgpr(s16) = G_ANYEXT %1
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%3:vgpr(s32) = G_ZEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: anyext_vgpr_s1_to_vgpr_s32
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legalized: true
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regBankSelected: true

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir

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Original file line numberDiff line numberDiff line change
@@ -3,6 +3,27 @@
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44
---
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name: sext_sgpr_s1_to_sgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s16
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
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; GCN-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[S_BFE_I32_]], 1048576, implicit-def $scc
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; GCN-NEXT: $sgpr0 = COPY [[S_BFE_U32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s16) = G_SEXT %1
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%3:sgpr(s32) = G_ZEXT %2
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$sgpr0 = COPY %3
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...
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---
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name: sext_sgpr_s1_to_sgpr_s32
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legalized: true
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regBankSelected: true
@@ -83,6 +104,27 @@ body: |
83104
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...
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---
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name: sext_sgpr_s32_to_sgpr_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: sext_sgpr_s32_to_sgpr_s64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 2097152, implicit-def $scc
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; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s64) = G_SEXT %0
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$sgpr0_sgpr1 = COPY %1
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...
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86128
# ---
87129

88130
# name: sext_vcc_s1_to_vgpr_s32
@@ -100,6 +142,27 @@ body: |
100142

101143
---
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name: sext_vgpr_s1_to_vgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: sext_vgpr_s1_to_vgpr_s16
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 1, implicit $exec
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; GCN-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[V_BFE_I32_e64_]], 0, 16, implicit $exec
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; GCN-NEXT: $vgpr0 = COPY [[V_BFE_U32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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%2:vgpr(s16) = G_SEXT %1
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%3:vgpr(s32) = G_ZEXT %2
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$vgpr0 = COPY %3
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...
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---
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103166
name: sext_vgpr_s1_to_vgpr_s32
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legalized: true
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regBankSelected: true

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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---
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name: zext_sgpr_s1_to_sgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s16
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
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; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_AND_B32_]]
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; GCN-NEXT: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s16) = G_ZEXT %1
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%3:sgpr(s32) = G_SEXT %2
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$sgpr0 = COPY %3
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...
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---
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name: zext_sgpr_s1_to_sgpr_s32
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legalized: true
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regBankSelected: true
@@ -83,6 +104,27 @@ body: |
83104
84105
...
85106

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---
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name: zext_sgpr_s32_to_sgpr_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: zext_sgpr_s32_to_sgpr_s64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 2097152, implicit-def $scc
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; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s64) = G_ZEXT %0
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$sgpr0_sgpr1 = COPY %1
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...
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86128
# ---
87129

88130
# name: zext_vcc_s1_to_vgpr_s32
@@ -100,6 +142,27 @@ body: |
100142

101143
---
102144

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name: zext_vgpr_s1_to_vgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s16
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
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; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[V_AND_B32_e32_]], 0, 16, implicit $exec
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; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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%2:vgpr(s16) = G_ZEXT %1
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%3:vgpr(s32) = G_SEXT %2
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$vgpr0 = COPY %3
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...
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---
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103166
name: zext_vgpr_s1_to_vgpr_s32
104167
legalized: true
105168
regBankSelected: true

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