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[AMDGPU][GlobalISel] Regenerate checks in inst-select-*ext.mir
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3 files changed

+66
-62
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3 files changed

+66
-62
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir

Lines changed: 30 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ body: |
1313
1414
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
1515
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
16-
; GCN: $sgpr0 = COPY [[COPY]]
16+
; GCN-NEXT: $sgpr0 = COPY [[COPY]]
1717
%0:sgpr(s32) = COPY $sgpr0
1818
%1:sgpr(s16) = G_TRUNC %0
1919
%2:sgpr(s32) = G_ANYEXT %1
@@ -22,7 +22,7 @@ body: |
2222
...
2323

2424
---
25-
name: anyext_sgpr_s32_to_sgpr_s64
25+
name: anyext_sgpr_s32_to_sgpr_s64
2626
legalized: true
2727
regBankSelected: true
2828
tracksRegLiveness: true
@@ -32,18 +32,19 @@ body: |
3232
3333
; GCN-LABEL: name: anyext_sgpr_s32_to_sgpr_s64
3434
; GCN: liveins: $sgpr0
35-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
36-
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
37-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
38-
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
35+
; GCN-NEXT: {{ $}}
36+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
37+
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
38+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
39+
; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
3940
%0:sgpr(s32) = COPY $sgpr0
4041
%1:sgpr(s64) = G_ANYEXT %0
4142
S_ENDPGM 0, implicit %1
4243
4344
...
4445

4546
---
46-
name: anyext_sgpr_s16_to_sgpr_s64
47+
name: anyext_sgpr_s16_to_sgpr_s64
4748
legalized: true
4849
regBankSelected: true
4950
tracksRegLiveness: true
@@ -53,10 +54,11 @@ body: |
5354
5455
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
5556
; GCN: liveins: $sgpr0
56-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
57-
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
58-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
59-
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
57+
; GCN-NEXT: {{ $}}
58+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
59+
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
60+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
61+
; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
6062
%0:sgpr(s32) = COPY $sgpr0
6163
%1:sgpr(s16) = G_TRUNC %0
6264
%2:sgpr(s64) = G_ANYEXT %1
@@ -65,7 +67,7 @@ body: |
6567
...
6668

6769
---
68-
name: anyext_vgpr_s32_to_vgpr_s64
70+
name: anyext_vgpr_s32_to_vgpr_s64
6971
legalized: true
7072
regBankSelected: true
7173
tracksRegLiveness: true
@@ -75,18 +77,19 @@ body: |
7577
7678
; GCN-LABEL: name: anyext_vgpr_s32_to_vgpr_s64
7779
; GCN: liveins: $vgpr0
78-
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
79-
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
80-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
81-
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
80+
; GCN-NEXT: {{ $}}
81+
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
82+
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
83+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
84+
; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
8285
%0:vgpr(s32) = COPY $vgpr0
8386
%1:vgpr(s64) = G_ANYEXT %0
8487
S_ENDPGM 0, implicit %1
8588
8689
...
8790

8891
---
89-
name: anyext_vgpr_s16_to_vgpr_s64
92+
name: anyext_vgpr_s16_to_vgpr_s64
9093
legalized: true
9194
regBankSelected: true
9295
tracksRegLiveness: true
@@ -96,10 +99,11 @@ body: |
9699
97100
; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
98101
; GCN: liveins: $vgpr0
99-
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
100-
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
101-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
102-
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
102+
; GCN-NEXT: {{ $}}
103+
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
104+
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
105+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
106+
; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
103107
%0:vgpr(s32) = COPY $vgpr0
104108
%1:vgpr(s16) = G_TRUNC %0
105109
%2:vgpr(s64) = G_ANYEXT %1
@@ -134,7 +138,7 @@ body: |
134138
135139
; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
136140
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
137-
; GCN: $sgpr0 = COPY [[COPY]]
141+
; GCN-NEXT: $sgpr0 = COPY [[COPY]]
138142
%0:sgpr(s32) = COPY $sgpr0
139143
%1:sgpr(s1) = G_TRUNC %0
140144
%2:sgpr(s32) = G_ANYEXT %1
@@ -152,7 +156,7 @@ body: |
152156
153157
; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
154158
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
155-
; GCN: $vgpr0 = COPY [[COPY]]
159+
; GCN-NEXT: $vgpr0 = COPY [[COPY]]
156160
%0:vgpr(s32) = COPY $vgpr0
157161
%1:vgpr(s1) = G_TRUNC %0
158162
%2:vgpr(s32) = G_ANYEXT %1
@@ -170,7 +174,7 @@ body: |
170174
171175
; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32
172176
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
173-
; GCN: $sgpr0 = COPY [[COPY]]
177+
; GCN-NEXT: $sgpr0 = COPY [[COPY]]
174178
%0:sgpr(s32) = COPY $sgpr0
175179
%1:sgpr(s1) = G_TRUNC %0
176180
%2:sgpr(s32) = G_ANYEXT %1
@@ -188,7 +192,7 @@ body: |
188192
189193
; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
190194
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
191-
; GCN: $vgpr0 = COPY [[COPY]]
195+
; GCN-NEXT: $vgpr0 = COPY [[COPY]]
192196
%0:vgpr(s32) = COPY $vgpr0
193197
%1:vgpr(s16) = G_TRUNC %0
194198
%2:vgpr(s32) = G_ANYEXT %1
@@ -209,7 +213,7 @@ body: |
209213
210214
; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32
211215
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
212-
; GCN: $sgpr0 = COPY [[COPY]]
216+
; GCN-NEXT: $sgpr0 = COPY [[COPY]]
213217
%0:sgpr(s32) = COPY $sgpr0
214218
%1:sreg_32(s1) = G_TRUNC %0
215219
%2:sgpr(s32) = G_ANYEXT %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@ body: |
1212
1313
; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s32
1414
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
15-
; GCN: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
16-
; GCN: $sgpr0 = COPY [[S_BFE_I32_]]
15+
; GCN-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
16+
; GCN-NEXT: $sgpr0 = COPY [[S_BFE_I32_]]
1717
%0:sgpr(s32) = COPY $sgpr0
1818
%1:sgpr(s1) = G_TRUNC %0
1919
%2:sgpr(s32) = G_SEXT %1
@@ -31,10 +31,10 @@ body: |
3131
3232
; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s64
3333
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
34-
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
35-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
36-
; GCN: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 65536, implicit-def $scc
37-
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
34+
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
35+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
36+
; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 65536, implicit-def $scc
37+
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
3838
%0:sgpr(s32) = COPY $sgpr0
3939
%1:sgpr(s1) = G_TRUNC %0
4040
%2:sgpr(s64) = G_SEXT %1
@@ -52,8 +52,8 @@ body: |
5252
5353
; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s32
5454
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
55-
; GCN: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[COPY]]
56-
; GCN: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
55+
; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[COPY]]
56+
; GCN-NEXT: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
5757
%0:sgpr(s32) = COPY $sgpr0
5858
%1:sgpr(s16) = G_TRUNC %0
5959
%2:sgpr(s32) = G_SEXT %1
@@ -72,10 +72,10 @@ body: |
7272
7373
; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s64
7474
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
75-
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
76-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
77-
; GCN: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
78-
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
75+
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
76+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
77+
; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
78+
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
7979
%0:sgpr(s32) = COPY $sgpr0
8080
%1:sgpr(s16) = G_TRUNC %0
8181
%2:sgpr(s64) = G_SEXT %1
@@ -109,8 +109,8 @@ body: |
109109
110110
; GCN-LABEL: name: sext_vgpr_s1_to_vgpr_s32
111111
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
112-
; GCN: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 1, implicit $exec
113-
; GCN: $vgpr0 = COPY [[V_BFE_I32_e64_]]
112+
; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 1, implicit $exec
113+
; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
114114
%0:vgpr(s32) = COPY $vgpr0
115115
%1:vgpr(s1) = G_TRUNC %0
116116
%2:vgpr(s32) = G_SEXT %1
@@ -128,8 +128,8 @@ body: |
128128
129129
; GCN-LABEL: name: sext_vgpr_s16_to_vgpr_s32
130130
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
131-
; GCN: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 16, implicit $exec
132-
; GCN: $vgpr0 = COPY [[V_BFE_I32_e64_]]
131+
; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 16, implicit $exec
132+
; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
133133
%0:vgpr(s32) = COPY $vgpr0
134134
%1:vgpr(s16) = G_TRUNC %0
135135
%2:vgpr(s32) = G_SEXT %1
@@ -148,8 +148,8 @@ body: |
148148
149149
; GCN-LABEL: name: sext_sgpr_reg_class_s1_to_sgpr_s32
150150
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
151-
; GCN: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
152-
; GCN: $sgpr0 = COPY [[S_BFE_I32_]]
151+
; GCN-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
152+
; GCN-NEXT: $sgpr0 = COPY [[S_BFE_I32_]]
153153
%0:sgpr(s32) = COPY $sgpr0
154154
%1:sreg_32(s1) = G_TRUNC %0
155155
%2:sgpr(s32) = G_SEXT %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@ body: |
1212
1313
; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
1414
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
15-
; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
16-
; GCN: $sgpr0 = COPY [[S_AND_B32_]]
15+
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
16+
; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
1717
%0:sgpr(s32) = COPY $sgpr0
1818
%1:sgpr(s1) = G_TRUNC %0
1919
%2:sgpr(s32) = G_ZEXT %1
@@ -31,10 +31,10 @@ body: |
3131
3232
; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
3333
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
34-
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
35-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
36-
; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
37-
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
34+
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
35+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
36+
; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
37+
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
3838
%0:sgpr(s32) = COPY $sgpr0
3939
%1:sgpr(s1) = G_TRUNC %0
4040
%2:sgpr(s64) = G_ZEXT %1
@@ -52,8 +52,8 @@ body: |
5252
5353
; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
5454
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
55-
; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
56-
; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
55+
; GCN-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
56+
; GCN-NEXT: $sgpr0 = COPY [[S_BFE_U32_]]
5757
%0:sgpr(s32) = COPY $sgpr0
5858
%1:sgpr(s16) = G_TRUNC %0
5959
%2:sgpr(s32) = G_ZEXT %1
@@ -72,10 +72,10 @@ body: |
7272
7373
; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
7474
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
75-
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
76-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
77-
; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
78-
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
75+
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
76+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
77+
; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
78+
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
7979
%0:sgpr(s32) = COPY $sgpr0
8080
%1:sgpr(s16) = G_TRUNC %0
8181
%2:sgpr(s64) = G_ZEXT %1
@@ -109,8 +109,8 @@ body: |
109109
110110
; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
111111
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
112-
; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
113-
; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
112+
; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
113+
; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e32_]]
114114
%0:vgpr(s32) = COPY $vgpr0
115115
%1:vgpr(s1) = G_TRUNC %0
116116
%2:vgpr(s32) = G_ZEXT %1
@@ -128,8 +128,8 @@ body: |
128128
129129
; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32
130130
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
131-
; GCN: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
132-
; GCN: $vgpr0 = COPY [[V_BFE_U32_e64_]]
131+
; GCN-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
132+
; GCN-NEXT: $vgpr0 = COPY [[V_BFE_U32_e64_]]
133133
%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s32) = G_ZEXT %1
@@ -148,8 +148,8 @@ body: |
148148
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; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
151-
; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
152-
; GCN: $sgpr0 = COPY [[S_AND_B32_]]
151+
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
152+
; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sreg_32(s1) = G_TRUNC %0
155155
%2:sgpr(s32) = G_ZEXT %1

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