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burrbullburrbull
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move pin traits in gpio::alt & pwm::into_complementary/with_break_pin
1 parent 24e2847 commit 6c14ae4

23 files changed

+6150
-4409
lines changed

‎Cargo.toml

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,10 @@ required-features = ["rt", "rtc"]
250250
name = "sai_dma_passthru"
251251
required-features = ["rm0433"]
252252

253+
[[example]]
254+
name = "spi-dma"
255+
required-features = ["rm0433"]
256+
253257
[[example]]
254258
name = "spi-dma-rtic"
255259
required-features = ["rm0433","rt"]

‎examples/fmc.rs

Lines changed: 35 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -15,20 +15,19 @@ mod utilities;
1515
extern crate cortex_m;
1616

1717
use cortex_m_rt::entry;
18-
use stm32h7xx_hal::gpio::Speed;
18+
use stm32h7xx_hal::gpio::{alt::fmc as alt, Speed};
1919
use stm32h7xx_hal::{pac, prelude::*};
2020

2121
use stm32_fmc::devices::is42s32800g_6;
2222

2323
/// Configre a pin for the FMC controller
2424
macro_rules! fmc_pins {
25-
($($pin:expr),*) => {
25+
($($alt:ty: $pin:expr),*) => {
2626
(
2727
$(
28-
$pin.into_push_pull_output()
28+
<$alt>::from($pin.into_alternate()
2929
.speed(Speed::VeryHigh)
30-
.into_alternate::<12>()
31-
.internal_pull_up(true)
30+
.internal_pull_up(true))
3231
),*
3332
)
3433
};
@@ -156,28 +155,40 @@ fn main() -> ! {
156155
// Initialise SDRAM...
157156
let sdram_pins = fmc_pins! {
158157
// A0-A11
159-
gpiof.pf0, gpiof.pf1, gpiof.pf2, gpiof.pf3,
160-
gpiof.pf4, gpiof.pf5, gpiof.pf12, gpiof.pf13,
161-
gpiof.pf14, gpiof.pf15, gpiog.pg0, gpiog.pg1,
158+
alt::A0: gpiof.pf0, alt::A1: gpiof.pf1,
159+
alt::A2: gpiof.pf2, alt::A3: gpiof.pf3,
160+
alt::A4: gpiof.pf4, alt::A5: gpiof.pf5,
161+
alt::A6: gpiof.pf12, alt::A7: gpiof.pf13,
162+
alt::A8: gpiof.pf14, alt::A9: gpiof.pf15,
163+
alt::A10: gpiog.pg0, alt::A11: gpiog.pg1,
162164
// BA0-BA1
163-
gpiog.pg4, gpiog.pg5,
165+
alt::Ba0: gpiog.pg4, alt::Ba1: gpiog.pg5,
164166
// D0-D31
165-
gpiod.pd14, gpiod.pd15, gpiod.pd0, gpiod.pd1,
166-
gpioe.pe7, gpioe.pe8, gpioe.pe9, gpioe.pe10,
167-
gpioe.pe11, gpioe.pe12, gpioe.pe13, gpioe.pe14,
168-
gpioe.pe15, gpiod.pd8, gpiod.pd9, gpiod.pd10,
169-
gpioh.ph8, gpioh.ph9, gpioh.ph10, gpioh.ph11,
170-
gpioh.ph12, gpioh.ph13, gpioh.ph14, gpioh.ph15,
171-
gpioi.pi0, gpioi.pi1, gpioi.pi2, gpioi.pi3,
172-
gpioi.pi6, gpioi.pi7, gpioi.pi9, gpioi.pi10,
167+
alt::D0: gpiod.pd14, alt::D1: gpiod.pd15,
168+
alt::D2: gpiod.pd0, alt::D3: gpiod.pd1,
169+
alt::D4: gpioe.pe7, alt::D5: gpioe.pe8,
170+
alt::D6: gpioe.pe9, alt::D7: gpioe.pe10,
171+
alt::D8: gpioe.pe11, alt::D9: gpioe.pe12,
172+
alt::D10: gpioe.pe13, alt::D11: gpioe.pe14,
173+
alt::D12: gpioe.pe15, alt::D13: gpiod.pd8,
174+
alt::D14: gpiod.pd9, alt::D15: gpiod.pd10,
175+
alt::D16: gpioh.ph8, alt::D17: gpioh.ph9,
176+
alt::D18: gpioh.ph10, alt::D19: gpioh.ph11,
177+
alt::D20: gpioh.ph12, alt::D21: gpioh.ph13,
178+
alt::D22: gpioh.ph14, alt::D23: gpioh.ph15,
179+
alt::D24: gpioi.pi0, alt::D25: gpioi.pi1,
180+
alt::D26: gpioi.pi2, alt::D27: gpioi.pi3,
181+
alt::D28: gpioi.pi6, alt::D29: gpioi.pi7,
182+
alt::D30: gpioi.pi9, alt::D31: gpioi.pi10,
173183
// NBL0 - NBL3
174-
gpioe.pe0, gpioe.pe1, gpioi.pi4, gpioi.pi5,
175-
gpioh.ph7, // SDCKE1
176-
gpiog.pg8, // SDCLK
177-
gpiog.pg15, // SDNCAS
178-
gpioh.ph6, // SDNE1 (!CS)
179-
gpiof.pf11, // SDRAS
180-
gpioh.ph5 // SDNWE
184+
alt::Nbl0: gpioe.pe0, alt::Nbl1: gpioe.pe1,
185+
alt::Nbl2: gpioi.pi4, alt::Nbl3: gpioi.pi5,
186+
alt::Sdcke1: gpioh.ph7,
187+
alt::Sdclk: gpiog.pg8,
188+
alt::Sdncas: gpiog.pg15,
189+
alt::Sdne1: gpioh.ph6,
190+
alt::Sdnras: gpiof.pf11, // SDRAS
191+
alt::Sdnwe: gpioh.ph5 // SDNWE
181192
};
182193

183194
let mut sdram = dp.FMC.sdram(

‎examples/fmc_nand_flash.rs

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -15,21 +15,20 @@ use log::info;
1515
extern crate cortex_m;
1616

1717
use cortex_m_rt::entry;
18-
use stm32h7xx_hal::gpio::Speed;
18+
use stm32h7xx_hal::gpio::{alt::fmc as alt, Speed};
1919
use stm32h7xx_hal::{pac, prelude::*, rcc::rec};
2020

2121
use stm32_fmc::devices::s34ml08g3_4kb;
2222
use stm32_fmc::nand_device::Status;
2323

2424
/// Configre a pin for the FMC controller
2525
macro_rules! fmc_pins {
26-
($($pin:expr),*) => {
26+
($($alt:ty: $pin:expr),*) => {
2727
(
2828
$(
29-
$pin.into_push_pull_output()
29+
<$alt>::from($pin.into_alternate()
3030
.speed(Speed::VeryHigh)
31-
.into_alternate::<12>()
32-
.internal_pull_up(true)
31+
.internal_pull_up(true))
3332
),*
3433
)
3534
};
@@ -71,21 +70,22 @@ fn main() -> ! {
7170
// Initialise NAND Flash...
7271
let nand_flash_pins = fmc_pins! {
7372
// A17/ALE; A16/CLE
74-
gpiod.pd12, gpiod.pd11,
73+
alt::A17: gpiod.pd12,
74+
alt::A16: gpiod.pd11,
7575
// D0-D7
76-
gpiod.pd14,
77-
gpiod.pd15,
78-
gpiod.pd0,
79-
gpiod.pd1,
80-
gpioe.pe7,
81-
gpioe.pe8,
82-
gpioe.pe9,
83-
gpioe.pe10,
76+
alt::D0: gpiod.pd14,
77+
alt::D1: gpiod.pd15,
78+
alt::D2: gpiod.pd0,
79+
alt::D3: gpiod.pd1,
80+
alt::D4: gpioe.pe7,
81+
alt::D5: gpioe.pe8,
82+
alt::D6: gpioe.pe9,
83+
alt::D7: gpioe.pe10,
8484
//
85-
gpiog.pg9, // NCE
86-
gpiod.pd4, // NOE
87-
gpiod.pd5, // NWE
88-
gpiod.pd6 // NWAIT
85+
alt::Nce: gpiog.pg9,
86+
alt::Noe: gpiod.pd4,
87+
alt::Nwe: gpiod.pd5,
88+
alt::Nwait: gpiod.pd6
8989
};
9090
gpioe.pe2.into_push_pull_output().set_high(); // unprotect
9191

‎examples/pwm_advanced.rs

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -107,18 +107,14 @@ fn main() -> ! {
107107
.prescaler(39)
108108
.period(49_999)
109109
.with_deadtime(1.millis())
110-
.with_break_pin(gpioe.pe15.into_alternate(), Polarity::ActiveLow)
110+
.with_break_pin(gpioe.pe15, Polarity::ActiveLow)
111111
.center_aligned();
112112

113113
let (mut t1control, (t1c4, t1c2, t1c1, t1c3)) = t1builder.finalize();
114114

115-
let mut t1c1 = t1c1.into_complementary(gpioe.pe8.into_alternate());
116-
let mut t1c2 = t1c2
117-
.into_complementary(gpioe.pe10.into_alternate())
118-
.into_active_low();
119-
let mut t1c3 = t1c3
120-
.into_complementary(gpioe.pe12.into_alternate())
121-
.into_comp_active_low();
115+
let mut t1c1 = t1c1.into_complementary(gpioe.pe8);
116+
let mut t1c2 = t1c2.into_complementary(gpioe.pe10).into_active_low();
117+
let mut t1c3 = t1c3.into_complementary(gpioe.pe12).into_comp_active_low();
122118
let mut t1c4 = t1c4.into_active_low();
123119

124120
// Output TIM1 PWM
@@ -238,12 +234,12 @@ fn main() -> ! {
238234
)
239235
.frequency(4.kHz())
240236
.with_deadtime(2.micros())
241-
.with_break_pin(gpiog.pg3.into_alternate(), Polarity::ActiveHigh)
237+
.with_break_pin2(gpiog.pg3, Polarity::ActiveHigh)
242238
.right_aligned()
243239
.finalize();
244240

245-
let mut t8c1 = t8c1.into_complementary(gpioa.pa5.into_alternate());
246-
let mut t8c3 = t8c3.into_complementary(gpiob.pb1.into_alternate());
241+
let mut t8c1 = t8c1.into_complementary(gpioa.pa5);
242+
let mut t8c3 = t8c3.into_complementary(gpiob.pb1);
247243
let mut t8c4 = t8c4.into_active_low();
248244

249245
// Output TIM8 PWM
@@ -321,12 +317,12 @@ fn main() -> ! {
321317
&ccdr.clocks,
322318
)
323319
.frequency(500.kHz())
324-
.with_break_pin(gpioe.pe3.into_alternate(), Polarity::ActiveLow)
320+
.with_break_pin(gpioe.pe3, Polarity::ActiveLow)
325321
.left_aligned()
326322
.finalize();
327323

328324
let mut t15c1 = t15c1
329-
.into_complementary(gpioe.pe4.into_alternate())
325+
.into_complementary(gpioe.pe4)
330326
.into_active_low()
331327
.into_comp_active_low();
332328

@@ -347,7 +343,7 @@ fn main() -> ! {
347343
&ccdr.clocks,
348344
)
349345
.frequency(500.kHz())
350-
.with_break_pin(gpiof.pf10.into_alternate(), Polarity::ActiveHigh)
346+
.with_break_pin(gpiof.pf10, Polarity::ActiveHigh)
351347
.finalize();
352348

353349
let mut t16c1 = t16c1.into_active_low();
@@ -370,7 +366,7 @@ fn main() -> ! {
370366
.with_deadtime(250.nanos())
371367
.finalize();
372368

373-
let mut t17c1 = t17c1.into_complementary(gpiof.pf9.into_alternate());
369+
let mut t17c1 = t17c1.into_complementary(gpiof.pf9);
374370

375371
// Output TIM16 PWM
376372
let period = t17c1.get_max_duty();

‎examples/qspi.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -30,21 +30,21 @@ fn main() -> ! {
3030
let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
3131
let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
3232

33-
let _qspi_cs = gpiog.pg6.into_alternate::<10>();
33+
let qspi_cs = gpiog.pg6;
3434

35-
let sck = gpiob.pb2.into_alternate();
36-
let io0 = gpiod.pd11.into_alternate();
37-
let io1 = gpiod.pd12.into_alternate();
38-
let io2 = gpioe.pe2.into_alternate();
39-
let io3 = gpiod.pd13.into_alternate();
35+
let sck = gpiob.pb2;
36+
let io0 = gpiod.pd11;
37+
let io1 = gpiod.pd12;
38+
let io2 = gpioe.pe2;
39+
let io3 = gpiod.pd13;
4040

4141
info!("");
4242
info!("stm32h7xx-hal example - QSPI");
4343
info!("");
4444

4545
// Initialise the QSPI peripheral.
4646
let mut qspi = dp.QUADSPI.bank1(
47-
(sck, io0, io1, io2, io3),
47+
(sck, io0, io1, io2, io3, Some(qspi_cs)),
4848
3.MHz(),
4949
&ccdr.clocks,
5050
ccdr.peripheral.QSPI,

‎examples/qspi_flash_memory.rs

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,6 @@
1111
mod utilities;
1212

1313
use cortex_m_rt::entry;
14-
use stm32h7xx_hal::gpio::Speed;
1514
use stm32h7xx_hal::{
1615
pac, prelude::*, xspi::Qspi, xspi::QspiMode, xspi::QspiWord,
1716
};
@@ -49,13 +48,13 @@ fn main() -> ! {
4948
let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
5049

5150
// Even though it is not directly used, CS pin must be acquired and configured
52-
let _qspi_cs = gpiog.pg6.into_alternate::<10>().speed(Speed::VeryHigh);
51+
let qspi_cs = gpiog.pg6;
5352

54-
let sck = gpiof.pf10.into_alternate().speed(Speed::VeryHigh);
55-
let io0 = gpiof.pf8.into_alternate().speed(Speed::VeryHigh);
56-
let io1 = gpiof.pf9.into_alternate().speed(Speed::VeryHigh);
57-
let io2 = gpiof.pf7.into_alternate().speed(Speed::VeryHigh);
58-
let io3 = gpiof.pf6.into_alternate().speed(Speed::VeryHigh);
53+
let sck = gpiof.pf10;
54+
let io0 = gpiof.pf8;
55+
let io1 = gpiof.pf9;
56+
let io2 = gpiof.pf7;
57+
let io3 = gpiof.pf6;
5958

6059
let mut led = gpioc.pc7.into_push_pull_output();
6160

@@ -65,7 +64,7 @@ fn main() -> ! {
6564

6665
// Initialise the QSPI peripheral
6766
let mut qspi = dp.QUADSPI.bank1(
68-
(sck, io0, io1, io2, io3),
67+
(sck, io0, io1, io2, io3, Some(qspi_cs)),
6968
3.MHz(),
7069
&ccdr.clocks,
7170
ccdr.peripheral.QSPI,

‎examples/qspi_mdma.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -45,13 +45,13 @@ fn main() -> ! {
4545
let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
4646
let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
4747

48-
let _qspi_cs = gpiog.pg6.into_alternate::<10>();
48+
let qspi_cs = gpiog.pg6;
4949

50-
let sck = gpiof.pf10.into_alternate();
51-
let io0 = gpiof.pf8.into_alternate();
52-
let io1 = gpiod.pd12.into_alternate();
53-
let io2 = gpioe.pe2.into_alternate();
54-
let io3 = gpiod.pd13.into_alternate();
50+
let sck = gpiof.pf10;
51+
let io0 = gpiof.pf8;
52+
let io1 = gpiod.pd12;
53+
let io2 = gpioe.pe2;
54+
let io3 = gpiod.pd13;
5555

5656
info!("");
5757
info!("stm32h7xx-hal example - QSPI with MDMA");
@@ -63,7 +63,7 @@ fn main() -> ! {
6363

6464
// Initialise the QSPI peripheral.
6565
let mut qspi = dp.QUADSPI.bank1(
66-
(sck, io0, io1, io2, io3),
66+
(sck, io0, io1, io2, io3, Some(qspi_cs)),
6767
config,
6868
&ccdr.clocks,
6969
ccdr.peripheral.QSPI,

‎examples/spi-dma-rtic.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ mod app {
7878
.communication_mode(hal::spi::CommunicationMode::Transmitter);
7979

8080
let spi: hal::spi::Spi<_, _, u8> = ctx.device.SPI2.spi(
81-
(sck, hal::spi::NoMiso, mosi),
81+
(sck, hal::spi::NoMiso::new(), mosi),
8282
config,
8383
3.MHz(),
8484
ccdr.peripheral.SPI2,

‎src/can.rs

Lines changed: 3 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -55,10 +55,7 @@ impl<FDCAN> Can<FDCAN> {
5555
}
5656
}
5757

58-
pub trait Instance: crate::Sealed {
59-
type Tx;
60-
type Rx;
61-
}
58+
pub trait Instance: crate::Sealed + crate::gpio::alt::CanCommon {}
6259

6360
/// Extension trait for CAN controller
6461
pub trait CanExt: Sized + Instance
@@ -151,14 +148,10 @@ macro_rules! message_ram_layout {
151148

152149
mod fdcan1 {
153150
use super::{rec, Can, CanExt, ResetEnable};
154-
use crate::gpio;
155151
use crate::stm32::FDCAN1;
156152

157153
impl crate::Sealed for FDCAN1 {}
158-
impl super::Instance for FDCAN1 {
159-
type Tx = gpio::alt::fdcan1::Tx;
160-
type Rx = gpio::alt::fdcan1::Rx;
161-
}
154+
impl super::Instance for FDCAN1 {}
162155

163156
impl Can<FDCAN1> {
164157
pub fn fdcan1(
@@ -194,14 +187,10 @@ mod fdcan1 {
194187

195188
mod fdcan2 {
196189
use super::{rec, Can, CanExt, ResetEnable};
197-
use crate::gpio;
198190
use crate::stm32::FDCAN2;
199191

200192
impl crate::Sealed for FDCAN2 {}
201-
impl super::Instance for FDCAN2 {
202-
type Tx = gpio::alt::fdcan2::Tx;
203-
type Rx = gpio::alt::fdcan2::Rx;
204-
}
193+
impl super::Instance for FDCAN2 {}
205194

206195
impl Can<FDCAN2> {
207196
pub fn fdcan2(

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