Use RTIC v0.5 alongside cortex-m v0.7

Using feature flag added in rtic-rs/rtic#509

Author: richardeoin

Cargo.toml

@@ -52,7 +52,7 @@ default-features = false
 optional = true
 
 [dev-dependencies]
-cortex-m-rtic = "0.5.3"
+cortex-m-rtic = { version = "0.5.8", default-features = false, features = ["cortex-m-7"] }
 log = "0.4.11"
 panic-halt = "0.2.0"
 cfg-if = "0.1.10"

examples/rtic_low_power.rs

@@ -3,9 +3,10 @@
 //! After the end of init the CPU transitions into CStop mode, and D1/D2
 //! (aka. CD) transition into DStop mode.
 //!
-//! However we set the run_d3 flag, and enable Autonomous mode on the LPTIM3
-//! PREC struture. Therefore LPTIM3 continues to run and fires an interrupt that
-//! wakes the core. Following each interrupt the core returns to CStop mode.
+//! However we set the run_d3/run_srd flag, and enable Autonomous mode on the
+//! LPTIM3 PREC struture. Therefore LPTIM3 continues to run and fires an
+//! interrupt that wakes the core. Following each interrupt the core returns to
+//! CStop mode.
 //!
 //! On the first rising edge on PC13, the EXTI interrupt fires. We do not clear
 //! this interrupt, so we loop in the handler forever.
@@ -47,7 +48,10 @@ const APP: () = {
         let mut syscfg = ctx.device.SYSCFG;
 
         // Run D3 / SRD domain
+        #[cfg(not(feature = "rm0455"))]
         ctx.device.PWR.cpucr.modify(|_, w| w.run_d3().set_bit());
+        #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts
+        ctx.device.PWR.cpucr.modify(|_, w| w.run_srd().set_bit());
 
         let pwr = ctx.device.PWR.constrain();
         let vos = pwr.freeze();