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pac updates for RM0455 parts
1 parent 1cfee60 commit cbb803e

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8 files changed

+116
-23
lines changed

8 files changed

+116
-23
lines changed

‎CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
* **Breaking**: Simplified API for reading device signature
1111
values. `VAL::get().read()` becomes `VAL::read()`
1212
* adc: Allow parallel execution of multiple ADCs through `start_conversion()`
13+
* Rename the PeripheralREC object for BDMA2 on 7B3, 7B0, 7A3 parts from BDMA to BDMA2
1314

1415
## [v0.10.0] 2021-07-xx
1516

‎examples/i2c4_bdma.rs

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,10 @@ fn main() -> ! {
3737
let dp = pac::Peripherals::take().expect("Cannot take peripherals");
3838

3939
// Run D3 / SRD domain
40+
#[cfg(not(feature = "rm0455"))]
4041
dp.PWR.cpucr.modify(|_, w| w.run_d3().set_bit());
42+
#[cfg(feature = "rm0455")]
43+
dp.PWR.cpucr.modify(|_, w| w.run_srd().set_bit());
4144

4245
let pwr = dp.PWR.constrain();
4346
let pwrcfg = example_power!(pwr).freeze();
@@ -84,7 +87,7 @@ fn main() -> ! {
8487
#[cfg(feature = "rm0455")]
8588
let streams = StreamsTuple::new(
8689
dp.BDMA2,
87-
ccdr.peripheral.BDMA.low_power(LowPowerMode::Autonomous),
90+
ccdr.peripheral.BDMA2.low_power(LowPowerMode::Autonomous),
8891
);
8992

9093
let config = BdmaConfig::default().memory_increment(true);

‎src/dma/bdma.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ impl Instance for BDMA {
7070

7171
#[cfg(feature = "rm0455")]
7272
impl Instance for BDMA2 {
73-
type Rec = rec::Bdma;
73+
type Rec = rec::Bdma2;
7474

7575
#[inline(always)]
7676
fn ptr() -> *const BDMARegisterBlock {

‎src/pwr.rs

Lines changed: 50 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,30 @@ macro_rules! smps_level {
162162
$e.smpslevel()
163163
};
164164
}
165+
#[cfg(all(feature = "smps", not(feature = "rm0455")))]
166+
macro_rules! smps_en {
167+
($e:expr) => {
168+
$e.sden()
169+
};
170+
}
171+
#[cfg(all(feature = "smps", feature = "rm0455"))]
172+
macro_rules! smps_en {
173+
($e:expr) => {
174+
$e.smpsen()
175+
};
176+
}
177+
#[cfg(not(feature = "rm0455"))]
178+
macro_rules! d3cr {
179+
($e:expr) => {
180+
$e.d3cr
181+
};
182+
}
183+
#[cfg(feature = "rm0455")]
184+
macro_rules! d3cr {
185+
($e:expr) => {
186+
$e.srdcr
187+
};
188+
}
165189

166190
/// Internal power methods
167191
impl Pwr {
@@ -176,15 +200,19 @@ impl Pwr {
176200

177201
match self.supply_configuration {
178202
LDOSupply => {
179-
assert!(self.rb.cr3.read().sden().bit_is_clear(), "{}", error);
203+
assert!(
204+
smps_en!(self.rb.cr3.read()).bit_is_clear(),
205+
"{}",
206+
error
207+
);
180208
assert!(self.rb.cr3.read().ldoen().bit_is_set(), "{}", error);
181209
}
182210
DirectSMPS => {
183-
assert!(self.rb.cr3.read().sden().bit_is_set(), "{}", error);
211+
assert!(smps_en!(self.rb.cr3.read()).bit_is_set(), "{}", error);
184212
assert!(self.rb.cr3.read().ldoen().bit_is_clear(), "{}", error);
185213
}
186214
SMPSFeedsIntoLDO1V8 => {
187-
assert!(self.rb.cr3.read().sden().bit_is_set(), "{}", error);
215+
assert!(smps_en!(self.rb.cr3.read()).bit_is_set(), "{}", error);
188216
assert!(self.rb.cr3.read().ldoen().bit_is_clear(), "{}", error);
189217
assert!(
190218
smps_level!(self.rb.cr3.read()).bits() == 1,
@@ -193,7 +221,7 @@ impl Pwr {
193221
);
194222
}
195223
SMPSFeedsIntoLDO2V5 => {
196-
assert!(self.rb.cr3.read().sden().bit_is_set(), "{}", error);
224+
assert!(smps_en!(self.rb.cr3.read()).bit_is_set(), "{}", error);
197225
assert!(self.rb.cr3.read().ldoen().bit_is_clear(), "{}", error);
198226
assert!(
199227
smps_level!(self.rb.cr3.read()).bits() == 2,
@@ -202,7 +230,11 @@ impl Pwr {
202230
);
203231
}
204232
Bypass => {
205-
assert!(self.rb.cr3.read().sden().bit_is_clear(), "{}", error);
233+
assert!(
234+
smps_en!(self.rb.cr3.read()).bit_is_clear(),
235+
"{}",
236+
error
237+
);
206238
assert!(self.rb.cr3.read().ldoen().bit_is_clear(), "{}", error);
207239
assert!(self.rb.cr3.read().bypass().bit_is_set(), "{}", error);
208240
}
@@ -215,7 +247,7 @@ impl Pwr {
215247
///
216248
/// Does NOT implement overdrive (back-bias)
217249
fn voltage_scaling_transition(&self, new_scale: VoltageScale) {
218-
self.rb.d3cr.write(|w| unsafe {
250+
d3cr!(self.rb).write(|w| unsafe {
219251
// Manually set field values for each family
220252
w.vos().bits(
221253
#[cfg(not(feature = "rm0455"))]
@@ -236,7 +268,7 @@ impl Pwr {
236268
},
237269
)
238270
});
239-
while self.rb.d3cr.read().vosrdy().bit_is_clear() {}
271+
while d3cr!(self.rb).read().vosrdy().bit_is_clear() {}
240272
}
241273
}
242274

@@ -292,19 +324,22 @@ impl Pwr {
292324
use SupplyConfiguration::*;
293325

294326
match self.supply_configuration {
295-
LDOSupply => w.sden().clear_bit().ldoen().set_bit(),
296-
DirectSMPS => w.sden().set_bit().ldoen().clear_bit(),
327+
LDOSupply => smps_en!(w).clear_bit().ldoen().set_bit(),
328+
DirectSMPS => smps_en!(w).set_bit().ldoen().clear_bit(),
297329
SMPSFeedsIntoLDO1V8 => unsafe {
298-
let reg = w.sden().set_bit().ldoen().set_bit();
330+
let reg = smps_en!(w).set_bit().ldoen().set_bit();
299331
smps_level!(reg).bits(1)
300332
},
301333
SMPSFeedsIntoLDO2V5 => unsafe {
302-
let reg = w.sden().set_bit().ldoen().set_bit();
334+
let reg = smps_en!(w).set_bit().ldoen().set_bit();
303335
smps_level!(reg).bits(2)
304336
},
305-
Bypass => {
306-
w.sden().clear_bit().ldoen().clear_bit().bypass().set_bit()
307-
}
337+
Bypass => smps_en!(w)
338+
.clear_bit()
339+
.ldoen()
340+
.clear_bit()
341+
.bypass()
342+
.set_bit(),
308343
Default => {
309344
// Default configuration. The actual reset value of
310345
// CR3 varies between packages (See RM0399 Section
@@ -349,7 +384,7 @@ impl Pwr {
349384
unsafe {
350385
&(*SYSCFG::ptr()).pwrcr.modify(|_, w| w.oden().bits(1))
351386
};
352-
while self.rb.d3cr.read().vosrdy().bit_is_clear() {}
387+
while d3cr!(self.rb).read().vosrdy().bit_is_clear() {}
353388
vos = VoltageScale::Scale0;
354389
}
355390

‎src/rcc/backup.rs

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,8 +87,16 @@ mod rtc {
8787
// unsafe: Owned exclusive access to this bitfield
8888
interrupt::free(|_| {
8989
let bdcr = unsafe { &(*RCC::ptr()).bdcr };
90+
91+
#[cfg(not(feature = "rm0455"))]
9092
bdcr.modify(|_, w| w.bdrst().set_bit());
93+
#[cfg(not(feature = "rm0455"))]
9194
bdcr.modify(|_, w| w.bdrst().clear_bit());
95+
96+
#[cfg(feature = "rm0455")]
97+
bdcr.modify(|_, w| w.vswrst().set_bit());
98+
#[cfg(feature = "rm0455")]
99+
bdcr.modify(|_, w| w.vswrst().set_bit());
92100
});
93101
self
94102
}

‎src/rcc/mod.rs

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,11 +143,15 @@ use crate::pwr::PowerConfiguration;
143143
use crate::pwr::VoltageScale as Voltage;
144144
use crate::stm32::rcc::cfgr::SW_A as SW;
145145
use crate::stm32::rcc::cfgr::TIMPRE_A as TIMPRE;
146-
use crate::stm32::rcc::d1cfgr::HPRE_A as HPRE;
147146
use crate::stm32::rcc::pllckselr::PLLSRC_A as PLLSRC;
148147
use crate::stm32::{RCC, SYSCFG};
149148
use crate::time::Hertz;
150149

150+
#[cfg(feature = "rm0455")]
151+
use crate::stm32::rcc::cdcfgr1::HPRE_A as HPRE;
152+
#[cfg(not(feature = "rm0455"))]
153+
use crate::stm32::rcc::d1cfgr::HPRE_A as HPRE;
154+
151155
#[cfg(feature = "rm0455")]
152156
use crate::stm32::rcc::cdccipr::CKPERSEL_A as CKPERSEL;
153157
#[cfg(not(feature = "rm0455"))]
@@ -841,6 +845,7 @@ impl Rcc {
841845
}
842846

843847
// Core Prescaler / AHB Prescaler / APB3 Prescaler
848+
#[cfg(not(feature = "rm0455"))]
844849
rcc.d1cfgr.modify(|_, w| unsafe {
845850
w.d1cpre()
846851
.bits(d1cpre_bits)
@@ -849,23 +854,49 @@ impl Rcc {
849854
.hpre()
850855
.variant(hpre_bits)
851856
});
857+
#[cfg(feature = "rm0455")]
858+
rcc.cdcfgr1.modify(|_, w| unsafe {
859+
w.cdcpre()
860+
.bits(d1cpre_bits)
861+
.cdppre() // D1/CD contains APB3
862+
.bits(ppre3_bits)
863+
.hpre()
864+
.variant(hpre_bits)
865+
});
852866
// Ensure core prescaler value is valid before future lower
853867
// core voltage
868+
#[cfg(not(feature = "rm0455"))]
854869
while rcc.d1cfgr.read().d1cpre().bits() != d1cpre_bits {}
870+
#[cfg(feature = "rm0455")]
871+
while rcc.cdcfgr1.read().cdcpre().bits() != d1cpre_bits {}
855872

856873
// APB1 / APB2 Prescaler
874+
#[cfg(not(feature = "rm0455"))]
857875
rcc.d2cfgr.modify(|_, w| unsafe {
858876
w.d2ppre1() // D2 contains APB1
859877
.bits(ppre1_bits)
860878
.d2ppre2() // D2 also contains APB2
861879
.bits(ppre2_bits)
862880
});
881+
#[cfg(feature = "rm0455")]
882+
rcc.cdcfgr2.modify(|_, w| unsafe {
883+
w.cdppre1() // D2/CD contains APB1
884+
.bits(ppre1_bits)
885+
.cdppre2() // D2/CD also contains APB2
886+
.bits(ppre2_bits)
887+
});
863888

864889
// APB4 Prescaler
890+
#[cfg(not(feature = "rm0455"))]
865891
rcc.d3cfgr.modify(|_, w| unsafe {
866892
w.d3ppre() // D3 contains APB4
867893
.bits(ppre4_bits)
868894
});
895+
#[cfg(feature = "rm0455")]
896+
rcc.srdcfgr.modify(|_, w| unsafe {
897+
w.srdppre() // D3 contains APB4
898+
.bits(ppre4_bits)
899+
});
869900

870901
// Peripheral Clock (per_ck)
871902
#[cfg(not(feature = "rm0455"))]

‎src/rcc/rec.rs

Lines changed: 16 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -444,11 +444,18 @@ macro_rules! variant_return_type {
444444
}
445445

446446
// Register for autonomous mode enable bits
447+
#[cfg(not(feature = "rm0455"))]
447448
macro_rules! autonomous {
448449
($Auto:ident) => {
449450
&(*RCC::ptr()).d3amr
450451
};
451452
}
453+
#[cfg(feature = "rm0455")]
454+
macro_rules! autonomous {
455+
($Auto:ident) => {
456+
&(*RCC::ptr()).srdamr
457+
};
458+
}
452459

453460
// Enumerate all peripherals and optional clock multiplexers
454461
//
@@ -481,6 +488,7 @@ peripheral_reset_and_enable_control! {
481488
];
482489
#[cfg(feature = "rm0455")]
483490
AHB1, "" => [
491+
Crc,
484492
Usb1Otg [group clk: Usb cdccip2 "USB"],
485493
Adc12 [group clk: Adc(Variant) srdccip "ADC"]
486494
];
@@ -520,15 +528,18 @@ peripheral_reset_and_enable_control! {
520528

521529
#[cfg(all())]
522530
AHB4, "AMBA High-performance Bus (AHB4) peripherals" => [
523-
(Auto) Bdma,
524-
(Auto) Crc,
525-
526531
Gpioa, Gpiob, Gpioc, Gpiod, Gpioe, Gpiof, Gpiog, Gpioh, Gpioi, Gpioj, Gpiok
527532
];
528533
#[cfg(not(feature = "rm0455"))]
529534
AHB4, "" => [
535+
(Auto) Crc,
536+
(Auto) Bdma,
530537
(Auto) Adc3 [group clk: Adc]
531538
];
539+
#[cfg(feature = "rm0455")]
540+
AHB4, "" => [
541+
(Auto) Bdma2
542+
];
532543

533544

534545
#[cfg(all())]
@@ -579,17 +590,17 @@ peripheral_reset_and_enable_control! {
579590
#[cfg(feature = "rm0455")]
580591
APB1H, "" => [
581592
Fdcan [kernel clk: Fdcan(Variant) cdccip1 "FDCAN"],
582-
Swp [kernel clk: Swp cdccip1 "SWPMI"]
593+
Swpmi [kernel clk: Swpmi cdccip1 "SWPMI"]
583594
];
584595

585596

586597
#[cfg(all())]
587598
APB2, "Advanced Peripheral Bus 2 (APB2) peripherals" => [
588-
Hrtim,
589599
Tim1, Tim8, Tim15, Tim16, Tim17
590600
];
591601
#[cfg(not(feature = "rm0455"))]
592602
APB2, "" => [
603+
Hrtim,
593604
Dfsdm1 [kernel clk: Dfsdm1 d2ccip1 "DFSDM1"],
594605

595606
Sai1 [kernel clk: Sai1(Variant) d2ccip1 "SAI1"],

‎src/watchdog.rs

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,11 @@ impl SystemWindowWatchdog {
3535
/// to indicate the clock has not been used yet
3636
pub fn new(wwdg: WWDG, ccdr: &Ccdr) -> Self {
3737
// enable the peripheral inside the APB3
38+
#[cfg(not(feature = "rm0455"))]
3839
ccdr.rb.apb3enr.modify(|_, w| w.wwdg1en().set_bit());
40+
#[cfg(feature = "rm0455")]
41+
ccdr.rb.apb3enr.modify(|_, w| w.wwdgen().set_bit());
42+
3943
SystemWindowWatchdog {
4044
wwdg,
4145
down_counter: 0,

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