Merge #328

328: simplify alternate mode r=therealprof a=burrbull



Co-authored-by: Andrey Zgarbul <zgarbul.andrey@gmail.com>

Author: bors[bot]

CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Instead of `Alternate<AF1>` use just `Alternate<1>`.
 - `PinState` and `get/set_state`.
 - Inherent methods for infallible digital operations.
 - Generic `into_alternate` and `into_alternate_open_drain`. Non-generic ones are deprecated

examples/i2s-audio-out-dma.rs

@@ -216,10 +216,10 @@ type I2sDmaTransfer = Transfer<
         I2s<
             SPI3,
             (
-                PA4<Alternate<stm32f4xx_hal::gpio::AF6>>,
-                PC10<Alternate<stm32f4xx_hal::gpio::AF6>>,
-                PC7<Alternate<stm32f4xx_hal::gpio::AF6>>,
-                PC12<Alternate<stm32f4xx_hal::gpio::AF6>>,
+                PA4<Alternate<6>>,
+                PC10<Alternate<6>>,
+                PC7<Alternate<6>>,
+                PC12<Alternate<6>>,
             ),
         >,
         TransmitMode<Data16Frame16>,

src/can.rs

@@ -18,7 +18,7 @@ pub trait Pins: sealed::Sealed {
 /// The alternate function number can be specified after each pin name. If not specified, both
 /// default to AF9.
 macro_rules! pins {
-    ($($PER:ident => ($tx:ident<$txaf:ident>, $rx:ident<$rxaf:ident>),)+) => {
+    ($($PER:ident => ($tx:ident<$txaf:literal>, $rx:ident<$rxaf:literal>),)+) => {
         $(
             impl crate::can::sealed::Sealed for ($tx<crate::gpio::Alternate<$txaf>>, $rx<crate::gpio::Alternate<$rxaf>>) {}
             impl crate::can::Pins for ($tx<crate::gpio::Alternate<$txaf>>, $rx<crate::gpio::Alternate<$rxaf>>) {
@@ -27,7 +27,7 @@ macro_rules! pins {
         )+
     };
     ($($PER:ident => ($tx:ident, $rx:ident),)+) => {
-        pins! { $($PER => ($tx<crate::gpio::AF9>, $rx<crate::gpio::AF9>),)+ }
+        pins! { $($PER => ($tx<9>, $rx<9>),)+ }
     }
 }
 
@@ -36,56 +36,43 @@ mod common_pins {
         gpioa::{PA11, PA12},
         gpiob::{PB12, PB13, PB5, PB6},
         gpiod::{PD0, PD1},
-        AF9,
     };
     use crate::pac::{CAN1, CAN2};
     // All STM32F4 models with CAN support these pins
     pins! {
-        CAN1 => (PA12<AF9>, PA11<AF9>),
-        CAN1 => (PD1<AF9>, PD0<AF9>),
-        CAN2 => (PB13<AF9>, PB12<AF9>),
-        CAN2 => (PB6<AF9>, PB5<AF9>),
+        CAN1 => (PA12<9>, PA11<9>),
+        CAN1 => (PD1<9>, PD0<9>),
+        CAN2 => (PB13<9>, PB12<9>),
+        CAN2 => (PB6<9>, PB5<9>),
     }
 }
 
 #[cfg(any(feature = "stm32f412", feature = "stm32f413", feature = "stm32f423"))]
 mod pb9_pb8_af8 {
-    use crate::gpio::{
-        gpiob::{PB8, PB9},
-        AF8,
-    };
+    use crate::gpio::gpiob::{PB8, PB9};
     use crate::pac::CAN1;
-    pins! { CAN1 => (PB9<AF8>, PB8<AF8>), }
+    pins! { CAN1 => (PB9<8>, PB8<8>), }
 }
 
 #[cfg(any(feature = "can1", feature = "can2",))]
 mod pb9_pb8_af9 {
-    use crate::gpio::{
-        gpiob::{PB8, PB9},
-        AF9,
-    };
+    use crate::gpio::gpiob::{PB8, PB9};
     use crate::pac::CAN1;
-    pins! { CAN1 => (PB9<AF9>, PB8<AF9>), }
+    pins! { CAN1 => (PB9<9>, PB8<9>), }
 }
 
 #[cfg(any(feature = "stm32f412", feature = "stm32f413", feature = "stm32f423"))]
 mod pg1_pg0 {
-    use crate::gpio::{
-        gpiog::{PG0, PG1},
-        AF9,
-    };
+    use crate::gpio::gpiog::{PG0, PG1};
     use crate::pac::CAN1;
-    pins! { CAN1 => (PG1<AF9>, PG0<AF9>), }
+    pins! { CAN1 => (PG1<9>, PG0<9>), }
 }
 
 #[cfg(any(feature = "stm32f412", feature = "stm32f413", feature = "stm32f423"))]
 mod pg12_pg11 {
-    use crate::gpio::{
-        gpiog::{PG11, PG12},
-        AF9,
-    };
+    use crate::gpio::gpiog::{PG11, PG12};
     use crate::pac::CAN2;
-    pins! { CAN2 => (PG12<AF9>, PG11<AF9>), }
+    pins! { CAN2 => (PG12<9>, PG11<9>), }
 }
 
 #[cfg(any(
@@ -101,9 +88,9 @@ mod pg12_pg11 {
     feature = "stm32f479"
 ))]
 mod ph13_pi9 {
-    use crate::gpio::{gpioh::PH13, gpioi::PI9, AF9};
+    use crate::gpio::{gpioh::PH13, gpioi::PI9};
     use crate::pac::CAN1;
-    pins! { CAN1 => (PH13<AF9>, PI9<AF9>), }
+    pins! { CAN1 => (PH13<9>, PI9<9>), }
 }
 
 /// Pins and definitions for models with a third CAN peripheral
@@ -113,12 +100,11 @@ mod can3 {
     use crate::gpio::{
         gpioa::{PA15, PA8},
         gpiob::{PB3, PB4},
-        AF11,
     };
     use crate::pac::CAN3;
     pins! {
-        CAN3 => (PA15<AF11>, PA8<AF11>),
-        CAN3 => (PB4<AF11>, PB3<AF11>),
+        CAN3 => (PA15<11>, PA8<11>),
+        CAN3 => (PB4<11>, PB3<11>),
     }
 
     unsafe impl bxcan::Instance for Can<CAN3> {

src/fsmc_lcd/pins.rs

@@ -281,15 +281,15 @@ impl sealed::Conjure for (Lcd<SubBank1>, Lcd<SubBank2>, Lcd<SubBank3>, Lcd<SubBa
 /// # Example types that implement `ChipSelectPins`
 ///
 /// Wrapped single pins:
-/// * `ChipSelect1<PD7<Alternate<AF12>>>`
-/// * `ChipSelect2<PG9<Alternate<AF12>>>`
-/// * `ChipSelect3<PG10<Alternate<AF12>>>`
-/// * `ChipSelect4<PG12<Alternate<AF12>>>`
+/// * `ChipSelect1<PD7<Alternate<12>>>`
+/// * `ChipSelect2<PG9<Alternate<12>>>`
+/// * `ChipSelect3<PG10<Alternate<12>>>`
+/// * `ChipSelect4<PG12<Alternate<12>>>`
 ///
 /// Tuples of wrapped pins:
-/// * `(ChipSelect1<PD7<Alternate<AF12>>>, ChipSelect2<PG9<Alternate<AF12>>>)`
-/// * `(ChipSelect1<PD7<Alternate<AF12>>>, ChipSelect4<PG4<Alternate<AF12>>>)`
-/// * `(ChipSelect1<PD7<Alternate<AF12>>>, ChipSelect2<PG9<Alternate<AF12>>>, ChipSelect3<PG10<Alternate<AF12>>>, ChipSelect4<PG12<Alternate<AF12>>>)`
+/// * `(ChipSelect1<PD7<Alternate<12>>>, ChipSelect2<PG9<Alternate<12>>>)`
+/// * `(ChipSelect1<PD7<Alternate<12>>>, ChipSelect4<PG4<Alternate<12>>>)`
+/// * `(ChipSelect1<PD7<Alternate<12>>>, ChipSelect2<PG9<Alternate<12>>>, ChipSelect3<PG10<Alternate<12>>>, ChipSelect4<PG12<Alternate<12>>>)`
 pub trait ChipSelectPins: sealed::Sealed {
     /// One, two, three, or four `Lcd<_>` objects associated with the sub-bank(s) that these pin(s)
     /// control
@@ -605,10 +605,10 @@ mod common_pins {
     };
     use crate::gpio::gpiof::{PF0, PF1, PF12, PF13, PF14, PF15, PF2, PF3, PF4, PF5};
     use crate::gpio::gpiog::{PG0, PG1, PG10, PG12, PG13, PG2, PG3, PG4, PG5, PG9};
-    use crate::gpio::{Alternate, AF12};
+    use crate::gpio::Alternate;
 
     // All FSMC/FMC pins use AF12
-    type FmcAlternate = Alternate<AF12>;
+    type FmcAlternate = Alternate<12>;
 
     impl PinD2 for PD0<FmcAlternate> {}
     impl PinD3 for PD1<FmcAlternate> {}
@@ -687,7 +687,7 @@ mod common_pins {
     impl Sealed for PG12<FmcAlternate> {}
     impl PinAddress for PG13<FmcAlternate> {}
     impl Sealed for PG13<FmcAlternate> {}
-    // PG14<Alternate<AF12> can be used as address 25 (A25), but that pin is not available here.
+    // PG14<Alternate<12> can be used as address 25 (A25), but that pin is not available here.
     // Because external addresses are in units of 16 bits, external address line 25 can never
     // be high. The internal memory address would overflow into the next sub-bank.
 
@@ -725,39 +725,39 @@ mod extra_pins {
     use crate::gpio::gpiob::{PB12, PB14};
     use crate::gpio::gpioc::{PC11, PC12, PC2, PC3, PC4, PC5, PC6};
     use crate::gpio::gpiod::PD2;
-    use crate::gpio::{Alternate, AF10, AF12};
+    use crate::gpio::Alternate;
 
     // Most FSMC/FMC pins use AF12, but a few use AF10
-    type FmcAlternate = Alternate<AF12>;
+    type FmcAlternate = Alternate<12>;
 
     impl PinD4 for PA2<FmcAlternate> {}
     impl PinD5 for PA3<FmcAlternate> {}
     impl PinD6 for PA4<FmcAlternate> {}
     impl PinD7 for PA5<FmcAlternate> {}
     impl PinD13 for PB12<FmcAlternate> {}
-    impl PinD0 for PB14<Alternate<AF10>> {}
+    impl PinD0 for PB14<Alternate<10>> {}
     impl PinWriteEnable for PC2<FmcAlternate> {}
     impl PinAddress for PC3<FmcAlternate> {}
     impl Sealed for PC3<FmcAlternate> {}
     impl PinChipSelect4 for PC4<FmcAlternate> {}
     impl Sealed for PC4<FmcAlternate> {}
     impl PinReadEnable for PC5<FmcAlternate> {}
-    impl PinD1 for PC6<Alternate<AF10>> {}
-    impl PinD2 for PC11<Alternate<AF10>> {}
-    impl PinD3 for PC12<Alternate<AF10>> {}
-    impl PinWriteEnable for PD2<Alternate<AF10>> {}
+    impl PinD1 for PC6<Alternate<10>> {}
+    impl PinD2 for PC11<Alternate<10>> {}
+    impl PinD3 for PC12<Alternate<10>> {}
+    impl PinWriteEnable for PD2<Alternate<10>> {}
 
     // Sealed trait boilerplate
     impl Sealed for PA2<FmcAlternate> {}
     impl Sealed for PA3<FmcAlternate> {}
     impl Sealed for PA4<FmcAlternate> {}
     impl Sealed for PA5<FmcAlternate> {}
     impl Sealed for PB12<FmcAlternate> {}
-    impl Sealed for PB14<Alternate<AF10>> {}
+    impl Sealed for PB14<Alternate<10>> {}
     impl Sealed for PC2<FmcAlternate> {}
     impl Sealed for PC5<FmcAlternate> {}
-    impl Sealed for PC6<Alternate<AF10>> {}
-    impl Sealed for PC11<Alternate<AF10>> {}
-    impl Sealed for PC12<Alternate<AF10>> {}
-    impl Sealed for PD2<Alternate<AF10>> {}
+    impl Sealed for PC6<Alternate<10>> {}
+    impl Sealed for PC11<Alternate<10>> {}
+    impl Sealed for PC12<Alternate<10>> {}
+    impl Sealed for PD2<Alternate<10>> {}
 }