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Fix formatting
1 parent 9fa5940 commit 71a5cc0

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9 files changed

+31
-29
lines changed

9 files changed

+31
-29
lines changed

examples/can.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ use cortex_m_rt::entry;
1313

1414
use hal::prelude::*;
1515
use hal::stm32;
16-
use hal::watchdog::IndependentWatchDog;
1716
use hal::time::{duration::*, rate::*};
17+
use hal::watchdog::IndependentWatchDog;
1818

1919
use hal::can::{Can, CanFilter, CanFrame, CanId, Filter, Frame, Receiver, Transmitter};
2020
use nb::block;

examples/i2c_scanner.rs

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ use cortex_m::asm;
1616
use cortex_m_rt::entry;
1717
use cortex_m_semihosting::{hprint, hprintln};
1818

19-
use stm32f3xx_hal::{self as hal, pac, prelude::*};
2019
use hal::time::rate::*;
20+
use stm32f3xx_hal::{self as hal, pac, prelude::*};
2121

2222
const VALID_ADDR_RANGE: Range<u8> = 0x08..0x78;
2323

@@ -36,12 +36,14 @@ fn main() -> ! {
3636
gpiob.pb6.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SCL
3737
gpiob.pb7.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SDA
3838
);
39+
3940
let mut i2c = hal::i2c::I2c::new(
40-
dp.I2C1,
41-
pins,
42-
Hertz::try_from(100u32.kHz()).unwrap(),
43-
clocks,
44-
&mut rcc.apb1);
41+
dp.I2C1,
42+
pins,
43+
Hertz::try_from(100u32.kHz()).unwrap(),
44+
clocks,
45+
&mut rcc.apb1,
46+
);
4547

4648
hprintln!("Start i2c scanning...").expect("Error using hprintln.");
4749
hprintln!().unwrap();

examples/pwm.rs

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,10 @@ fn main() -> ! {
3030
// Configure our clocks
3131
let mut flash = dp.FLASH.constrain();
3232
let mut rcc = dp.RCC.constrain();
33-
let clocks = rcc.cfgr.sysclk(Hertz::try_from(16u32.MHz()).unwrap()).freeze(&mut flash.acr);
33+
let clocks = rcc
34+
.cfgr
35+
.sysclk(Hertz::try_from(16u32.MHz()).unwrap())
36+
.freeze(&mut flash.acr);
3437

3538
// Prep the pins we need in their correct alternate function
3639
let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
@@ -54,9 +57,9 @@ fn main() -> ! {
5457
// A four channel general purpose timer that's broadly available
5558
let tim3_channels = tim3(
5659
dp.TIM3,
57-
1280, // resolution of duty cycle
60+
1280, // resolution of duty cycle
5861
50u32.Hz(), // frequency of period
59-
&clocks, // To get the timer's clock speed
62+
&clocks, // To get the timer's clock speed
6063
);
6164

6265
// Channels without pins cannot be enabled, so we can't forget to
@@ -103,9 +106,9 @@ fn main() -> ! {
103106
// A 32-bit timer, so we can set a larger resolution
104107
let tim2_channels = tim2(
105108
dp.TIM2,
106-
160000, // resolution of duty cycle
109+
160000, // resolution of duty cycle
107110
50u32.Hz(), // frequency of period
108-
&clocks, // To get the timer's clock speed
111+
&clocks, // To get the timer's clock speed
109112
);
110113

111114
let mut tim2_ch3 = tim2_channels.2.output_to_pb10(pb10);
@@ -118,9 +121,9 @@ fn main() -> ! {
118121
// just use it directly
119122
let mut tim16_ch1 = tim16(
120123
dp.TIM16,
121-
1280, // resolution of duty cycle
124+
1280, // resolution of duty cycle
122125
50u32.Hz(), // frequency of period
123-
&clocks, // To get the timer's clock speed
126+
&clocks, // To get the timer's clock speed
124127
)
125128
.output_to_pb8(pb8);
126129
tim16_ch1.set_duty(tim16_ch1.get_max_duty() / 20); // 5% duty cyle
@@ -132,9 +135,9 @@ fn main() -> ! {
132135
// to complementary pins (works just like standard pins)
133136
let tim8_channels = tim8(
134137
dp.TIM8,
135-
1280, // resolution of duty cycle
138+
1280, // resolution of duty cycle
136139
50u32.Hz(), // frequency of period
137-
&clocks, // To get the timer's clock speed
140+
&clocks, // To get the timer's clock speed
138141
);
139142

140143
let mut tim8_ch1 = tim8_channels.0.output_to_pc10(pc10);

examples/serial_dma.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ use panic_semihosting as _;
99

1010
use cortex_m::{asm, singleton};
1111
use cortex_m_rt::entry;
12-
use stm32f3xx_hal::{pac, prelude::*, serial::Serial};
13-
use stm32f3xx_hal::time::rate::*;
12+
use stm32f3xx_hal::{pac, prelude::*, serial::Serial, time::rate::*};
1413

1514
#[entry]
1615
fn main() -> ! {

examples/usb_serial.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,8 @@ use core::convert::TryFrom;
1414

1515
use hal::pac;
1616
use hal::prelude::*;
17-
use hal::usb::{Peripheral, UsbBus};
1817
use hal::time::rate::*;
18+
use hal::usb::{Peripheral, UsbBus};
1919

2020
use usb_device::prelude::*;
2121
use usbd_serial::{SerialPort, USB_CLASS_CDC};

src/serial.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ use crate::{
55
hal::{blocking, serial},
66
pac::{USART1, USART2, USART3},
77
rcc::{Clocks, APB1, APB2},
8-
time::rate::Baud
8+
time::rate::Baud,
99
};
1010

1111
use cfg_if::cfg_if;

src/spi.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,8 +131,8 @@ use crate::rcc::APB1;
131131
feature = "stm32f398"
132132
))]
133133
use crate::rcc::APB2;
134-
use core::marker::PhantomData;
135134
use crate::time::rate::Hertz;
135+
use core::marker::PhantomData;
136136

137137
/// SPI error
138138
#[derive(Debug)]

src/timer.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,11 +50,9 @@ use crate::pac::{TIM15, TIM16, TIM17, TIM2, TIM6};
5050
feature = "stm32f398"
5151
))]
5252
use crate::pac::{TIM3, TIM7};
53-
54-
use void::Void;
55-
use crate::time::rate::Hertz;
5653
use crate::rcc::{Clocks, APB1, APB2};
57-
54+
use crate::time::rate::Hertz;
55+
use void::Void;
5856

5957
/// Associated clocks with timers
6058
pub trait PclkSrc {

tests/rcc.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ mod tests {
124124
let clock = rcc
125125
.cfgr
126126
.use_hse(Hertz::try_from(8u32.MHz()).unwrap())
127-
.sysclk( Hertz::try_from(48u32.MHz()).unwrap())
127+
.sysclk(Hertz::try_from(48u32.MHz()).unwrap())
128128
.freeze(&mut flash.acr); // works
129129

130130
defmt::assert!(clock.sysclk() == 48u32.MHz());
@@ -168,8 +168,8 @@ mod tests {
168168
let clock = rcc
169169
.cfgr
170170
.use_hse(Hertz::try_from(8u32.MHz()).unwrap())
171-
.pclk1( Hertz::try_from(16u32.MHz()).unwrap())
172-
.sysclk( Hertz::try_from(64u32.MHz()).unwrap())
171+
.pclk1(Hertz::try_from(16u32.MHz()).unwrap())
172+
.sysclk(Hertz::try_from(64u32.MHz()).unwrap())
173173
.freeze(&mut flash.acr);
174174

175175
defmt::assert!(clock.sysclk() == 64u32.MHz());
@@ -191,7 +191,7 @@ mod tests {
191191
let clock = rcc
192192
.cfgr
193193
.use_hse(Hertz::try_from(8u32.MHz()).unwrap())
194-
.sysclk( Hertz::try_from(72u32.MHz()).unwrap())
194+
.sysclk(Hertz::try_from(72u32.MHz()).unwrap())
195195
.freeze(&mut flash.acr);
196196

197197
defmt::assert!(clock.sysclk() == 72u32.MHz());

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