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Fix examples and tests
- Updated all examples to use embedded-time - Updated all tests to use embedded-time
1 parent 2c81f7e commit 9fa5940

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7 files changed

+98
-77
lines changed

7 files changed

+98
-77
lines changed

examples/can.rs

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,12 +6,15 @@ use panic_semihosting as _;
66

77
use stm32f3xx_hal as hal;
88

9+
use core::convert::TryFrom;
10+
911
use cortex_m::asm;
1012
use cortex_m_rt::entry;
1113

1214
use hal::prelude::*;
1315
use hal::stm32;
1416
use hal::watchdog::IndependentWatchDog;
17+
use hal::time::{duration::*, rate::*};
1518

1619
use hal::can::{Can, CanFilter, CanFrame, CanId, Filter, Frame, Receiver, Transmitter};
1720
use nb::block;
@@ -31,10 +34,10 @@ fn main() -> ! {
3134

3235
let _clocks = rcc
3336
.cfgr
34-
.use_hse(32.mhz())
35-
.sysclk(32.mhz())
36-
.pclk1(16.mhz())
37-
.pclk2(16.mhz())
37+
.use_hse(Hertz::try_from(32u32.MHz()).unwrap())
38+
.sysclk(Hertz::try_from(32u32.MHz()).unwrap())
39+
.pclk1(Hertz::try_from(16u32.MHz()).unwrap())
40+
.pclk2(Hertz::try_from(16u32.MHz()).unwrap())
3841
.freeze(&mut flash.acr);
3942

4043
// Configure CAN RX and TX pins (AF9)
@@ -60,7 +63,7 @@ fn main() -> ! {
6063
// Watchdog makes sure this gets restarted periodically if nothing happens
6164
let mut iwdg = IndependentWatchDog::new(dp.IWDG);
6265
iwdg.stop_on_debug(&dp.DBGMCU, true);
63-
iwdg.start(100.ms());
66+
iwdg.start(100u32.milliseconds());
6467

6568
// Send an initial message!
6669
asm::delay(100_000);

examples/i2c_scanner.rs

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,14 @@ use core::ops::Range;
1010

1111
use panic_semihosting as _;
1212

13+
use core::convert::TryFrom;
14+
1315
use cortex_m::asm;
1416
use cortex_m_rt::entry;
1517
use cortex_m_semihosting::{hprint, hprintln};
1618

1719
use stm32f3xx_hal::{self as hal, pac, prelude::*};
20+
use hal::time::rate::*;
1821

1922
const VALID_ADDR_RANGE: Range<u8> = 0x08..0x78;
2023

@@ -33,7 +36,12 @@ fn main() -> ! {
3336
gpiob.pb6.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SCL
3437
gpiob.pb7.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SDA
3538
);
36-
let mut i2c = hal::i2c::I2c::new(dp.I2C1, pins, 100.khz(), clocks, &mut rcc.apb1);
39+
let mut i2c = hal::i2c::I2c::new(
40+
dp.I2C1,
41+
pins,
42+
Hertz::try_from(100u32.kHz()).unwrap(),
43+
clocks,
44+
&mut rcc.apb1);
3745

3846
hprintln!("Start i2c scanning...").expect("Error using hprintln.");
3947
hprintln!().unwrap();

examples/pwm.rs

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@ use panic_semihosting as _;
77

88
use stm32f3xx_hal as hal;
99

10+
use core::convert::TryFrom;
11+
1012
use cortex_m::asm;
1113
use cortex_m_rt::entry;
1214

@@ -18,7 +20,7 @@ use hal::gpio::GpioExt;
1820
use hal::pac;
1921
use hal::pwm::{tim16, tim2, tim3, tim8};
2022
use hal::rcc::RccExt;
21-
use hal::time::U32Ext;
23+
use hal::time::rate::*;
2224

2325
#[entry]
2426
fn main() -> ! {
@@ -28,7 +30,7 @@ fn main() -> ! {
2830
// Configure our clocks
2931
let mut flash = dp.FLASH.constrain();
3032
let mut rcc = dp.RCC.constrain();
31-
let clocks = rcc.cfgr.sysclk(16.mhz()).freeze(&mut flash.acr);
33+
let clocks = rcc.cfgr.sysclk(Hertz::try_from(16u32.MHz()).unwrap()).freeze(&mut flash.acr);
3234

3335
// Prep the pins we need in their correct alternate function
3436
let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
@@ -53,7 +55,7 @@ fn main() -> ! {
5355
let tim3_channels = tim3(
5456
dp.TIM3,
5557
1280, // resolution of duty cycle
56-
50.hz(), // frequency of period
58+
50u32.Hz(), // frequency of period
5759
&clocks, // To get the timer's clock speed
5860
);
5961

@@ -102,7 +104,7 @@ fn main() -> ! {
102104
let tim2_channels = tim2(
103105
dp.TIM2,
104106
160000, // resolution of duty cycle
105-
50.hz(), // frequency of period
107+
50u32.Hz(), // frequency of period
106108
&clocks, // To get the timer's clock speed
107109
);
108110

@@ -117,7 +119,7 @@ fn main() -> ! {
117119
let mut tim16_ch1 = tim16(
118120
dp.TIM16,
119121
1280, // resolution of duty cycle
120-
50.hz(), // frequency of period
122+
50u32.Hz(), // frequency of period
121123
&clocks, // To get the timer's clock speed
122124
)
123125
.output_to_pb8(pb8);
@@ -131,7 +133,7 @@ fn main() -> ! {
131133
let tim8_channels = tim8(
132134
dp.TIM8,
133135
1280, // resolution of duty cycle
134-
50.hz(), // frequency of period
136+
50u32.Hz(), // frequency of period
135137
&clocks, // To get the timer's clock speed
136138
);
137139

examples/serial_dma.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ use panic_semihosting as _;
1010
use cortex_m::{asm, singleton};
1111
use cortex_m_rt::entry;
1212
use stm32f3xx_hal::{pac, prelude::*, serial::Serial};
13+
use stm32f3xx_hal::time::rate::*;
1314

1415
#[entry]
1516
fn main() -> ! {
@@ -25,7 +26,7 @@ fn main() -> ! {
2526
gpioa.pa9.into_af7(&mut gpioa.moder, &mut gpioa.afrh),
2627
gpioa.pa10.into_af7(&mut gpioa.moder, &mut gpioa.afrh),
2728
);
28-
let serial = Serial::usart1(dp.USART1, pins, 9600.bps(), clocks, &mut rcc.apb2);
29+
let serial = Serial::usart1(dp.USART1, pins, 9600.Bd(), clocks, &mut rcc.apb2);
2930
let (tx, rx) = serial.split();
3031

3132
let dma1 = dp.DMA1.split(&mut rcc.ahb);

examples/spi.rs

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,15 @@ use panic_semihosting as _;
77

88
use stm32f3xx_hal as hal;
99

10+
use core::convert::TryFrom;
11+
1012
use cortex_m::asm;
1113
use cortex_m_rt::entry;
1214

1315
use hal::pac;
1416
use hal::prelude::*;
1517
use hal::spi::{Mode, Phase, Polarity, Spi};
18+
use hal::time::rate::*;
1619

1720
#[entry]
1821
fn main() -> ! {
@@ -24,9 +27,9 @@ fn main() -> ! {
2427

2528
let clocks = rcc
2629
.cfgr
27-
.use_hse(8.mhz())
28-
.sysclk(48.mhz())
29-
.pclk1(24.mhz())
30+
.use_hse(Hertz::try_from(8u32.MHz()).unwrap())
31+
.sysclk(Hertz::try_from(48u32.MHz()).unwrap())
32+
.pclk1(Hertz::try_from(24u32.MHz()).unwrap())
3033
.freeze(&mut flash.acr);
3134

3235
// Configure pins for SPI
@@ -43,7 +46,7 @@ fn main() -> ! {
4346
dp.SPI1,
4447
(sck, miso, mosi),
4548
spi_mode,
46-
3.mhz(),
49+
Hertz::try_from(3u32.MHz()).unwrap(),
4750
clocks,
4851
&mut rcc.apb2,
4952
);

examples/usb_serial.rs

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,12 @@ use stm32f3xx_hal as hal;
1010
use cortex_m::asm::delay;
1111
use cortex_m_rt::entry;
1212

13+
use core::convert::TryFrom;
14+
1315
use hal::pac;
1416
use hal::prelude::*;
1517
use hal::usb::{Peripheral, UsbBus};
18+
use hal::time::rate::*;
1619

1720
use usb_device::prelude::*;
1821
use usbd_serial::{SerialPort, USB_CLASS_CDC};
@@ -26,10 +29,10 @@ fn main() -> ! {
2629

2730
let clocks = rcc
2831
.cfgr
29-
.use_hse(8.mhz())
30-
.sysclk(48.mhz())
31-
.pclk1(24.mhz())
32-
.pclk2(24.mhz())
32+
.use_hse(Hertz::try_from(8u32.MHz()).unwrap())
33+
.sysclk(Hertz::try_from(48u32.MHz()).unwrap())
34+
.pclk1(Hertz::try_from(24u32.MHz()).unwrap())
35+
.pclk2(Hertz::try_from(24u32.MHz()).unwrap())
3336
.freeze(&mut flash.acr);
3437

3538
assert!(clocks.usbclk_valid());

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