Return Result where Rate conversion may fail

Author: wbuck

examples/can.rs

@@ -6,8 +6,6 @@ use panic_semihosting as _;
 
 use stm32f3xx_hal as hal;
 
-use core::convert::TryFrom;
-
 use cortex_m::asm;
 use cortex_m_rt::entry;
 
@@ -34,10 +32,14 @@ fn main() -> ! {
 
     let _clocks = rcc
         .cfgr
-        .use_hse(Hertz::try_from(32u32.MHz()).unwrap())
-        .sysclk(Hertz::try_from(32u32.MHz()).unwrap())
-        .pclk1(Hertz::try_from(16u32.MHz()).unwrap())
-        .pclk2(Hertz::try_from(16u32.MHz()).unwrap())
+        .use_hse(32u32.MHz())
+        .unwrap()
+        .sysclk(32u32.MHz())
+        .unwrap()
+        .pclk1(16u32.MHz())
+        .unwrap()
+        .pclk2(16u32.MHz())
+        .unwrap()
         .freeze(&mut flash.acr);
 
     // Configure CAN RX and TX pins (AF9)

examples/i2c_scanner.rs

@@ -10,8 +10,6 @@ use core::ops::Range;
 
 use panic_semihosting as _;
 
-use core::convert::TryFrom;
-
 use cortex_m::asm;
 use cortex_m_rt::entry;
 use cortex_m_semihosting::{hprint, hprintln};
@@ -37,13 +35,7 @@ fn main() -> ! {
         gpiob.pb7.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SDA
     );
 
-    let mut i2c = hal::i2c::I2c::new(
-        dp.I2C1,
-        pins,
-        Hertz::try_from(100u32.kHz()).unwrap(),
-        clocks,
-        &mut rcc.apb1,
-    );
+    let mut i2c = hal::i2c::I2c::new(dp.I2C1, pins, 100u32.kHz(), clocks, &mut rcc.apb1).unwrap();
 
     hprintln!("Start i2c scanning...").expect("Error using hprintln.");
     hprintln!().unwrap();

examples/pwm.rs

@@ -7,8 +7,6 @@ use panic_semihosting as _;
 
 use stm32f3xx_hal as hal;
 
-use core::convert::TryFrom;
-
 use cortex_m::asm;
 use cortex_m_rt::entry;
 
@@ -30,10 +28,7 @@ fn main() -> ! {
     // Configure our clocks
     let mut flash = dp.FLASH.constrain();
     let mut rcc = dp.RCC.constrain();
-    let clocks = rcc
-        .cfgr
-        .sysclk(Hertz::try_from(16u32.MHz()).unwrap())
-        .freeze(&mut flash.acr);
+    let clocks = rcc.cfgr.sysclk(16u32.MHz()).unwrap().freeze(&mut flash.acr);
 
     // Prep the pins we need in their correct alternate function
     let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);

examples/spi.rs

@@ -7,8 +7,6 @@ use panic_semihosting as _;
 
 use stm32f3xx_hal as hal;
 
-use core::convert::TryFrom;
-
 use cortex_m::asm;
 use cortex_m_rt::entry;
 
@@ -27,9 +25,12 @@ fn main() -> ! {
 
     let clocks = rcc
         .cfgr
-        .use_hse(Hertz::try_from(8u32.MHz()).unwrap())
-        .sysclk(Hertz::try_from(48u32.MHz()).unwrap())
-        .pclk1(Hertz::try_from(24u32.MHz()).unwrap())
+        .use_hse(8u32.MHz())
+        .unwrap()
+        .sysclk(48u32.MHz())
+        .unwrap()
+        .pclk1(24u32.MHz())
+        .unwrap()
         .freeze(&mut flash.acr);
 
     // Configure pins for SPI
@@ -46,10 +47,11 @@ fn main() -> ! {
         dp.SPI1,
         (sck, miso, mosi),
         spi_mode,
-        Hertz::try_from(3u32.MHz()).unwrap(),
+        3u32.MHz(),
         clocks,
         &mut rcc.apb2,
-    );
+    )
+    .unwrap();
 
     // Create an `u8` array, which can be transfered via SPI.
     let msg_send: [u8; 8] = [0xD, 0xE, 0xA, 0xD, 0xB, 0xE, 0xE, 0xF];

examples/usb_serial.rs

@@ -10,8 +10,6 @@ use stm32f3xx_hal as hal;
 use cortex_m::asm::delay;
 use cortex_m_rt::entry;
 
-use core::convert::TryFrom;
-
 use hal::pac;
 use hal::prelude::*;
 use hal::time::rate::*;
@@ -29,10 +27,14 @@ fn main() -> ! {
 
     let clocks = rcc
         .cfgr
-        .use_hse(Hertz::try_from(8u32.MHz()).unwrap())
-        .sysclk(Hertz::try_from(48u32.MHz()).unwrap())
-        .pclk1(Hertz::try_from(24u32.MHz()).unwrap())
-        .pclk2(Hertz::try_from(24u32.MHz()).unwrap())
+        .use_hse(8u32.MHz())
+        .unwrap()
+        .sysclk(48u32.MHz())
+        .unwrap()
+        .pclk1(24u32.MHz())
+        .unwrap()
+        .pclk2(24u32.MHz())
+        .unwrap()
         .freeze(&mut flash.acr);
 
     assert!(clocks.usbclk_valid());

src/i2c.rs

@@ -4,15 +4,15 @@
 //!
 //! [examples/i2c_scanner.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.6.0/examples/i2c_scanner.rs
 
-use core::convert::TryFrom;
+use core::convert::{TryFrom, TryFrom};
 use core::ops::Deref;
 
 use crate::{
     gpio::{gpioa, gpiob, AF4},
     hal::blocking::i2c::{Read, Write, WriteRead},
     pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW_A, I2C1, RCC},
     rcc::{Clocks, APB1},
-    time::rate::Hertz,
+    time::rate::{Hertz, Rate},
 };
 
 #[cfg(not(feature = "gpio-f333"))]
@@ -111,14 +111,20 @@ macro_rules! busy_wait {
 
 impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
     /// Configures the I2C peripheral to work in master mode
-    pub fn new<F>(i2c: I2C, pins: (SCL, SDA), freq: F, clocks: Clocks, apb1: &mut APB1) -> Self
+    pub fn new<F>(
+        i2c: I2C,
+        pins: (SCL, SDA),
+        freq: F,
+        clocks: Clocks,
+        apb1: &mut APB1,
+    ) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
     where
         I2C: Instance,
         SCL: SclPin<I2C>,
         SDA: SdaPin<I2C>,
-        F: Into<Hertz>,
+        F: Rate + TryInto<Hertz<u32>>,
     {
-        let freq = freq.into().0;
+        let freq = (freq.try_into()? as Hertz).0;
 
         crate::assert!(freq <= 1_000_000);
 
@@ -195,7 +201,7 @@ impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
         // Enable the peripheral
         i2c.cr1.modify(|_, w| w.pe().set_bit());
 
-        Self { i2c, pins }
+        Ok(Self { i2c, pins })
     }
 
     /// Releases the I2C peripheral and associated pins

src/rcc.rs

@@ -54,13 +54,15 @@
 //! For more details read the documentation of the [`CFGR`] methods to
 //! find out how to setup the clock.
 
+use core::convert::TryInto;
+
 use crate::pac::{
     rcc::{self, cfgr, cfgr2},
     RCC,
 };
 
 use crate::flash::ACR;
-use crate::time::rate::Hertz;
+use crate::time::rate::{Hertz, Rate};
 
 /// Extension trait that constrains the `RCC` peripheral
 pub trait RccExt {
@@ -333,12 +335,12 @@ impl CFGR {
     ///
     /// Will result in a hang if an external oscillator is not connected or it fails to start,
     /// unless [css](CFGR::enable_css) is enabled.
-    pub fn use_hse<F>(mut self, freq: F) -> Self
+    pub fn use_hse<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
     where
-        F: Into<Hertz>,
+        F: Rate + TryInto<Hertz<u32>>,
     {
-        self.hse = Some(freq.into().0);
-        self
+        self.hse = Some((freq.try_into()? as Hertz).0);
+        Ok(self)
     }
 
     /// Enable `HSE` bypass.
@@ -364,12 +366,12 @@ impl CFGR {
     }
 
     /// Sets a frequency for the AHB bus
-    pub fn hclk<F>(mut self, freq: F) -> Self
+    pub fn hclk<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
     where
-        F: Into<Hertz>,
+        F: Rate + TryInto<Hertz<u32>>,
     {
-        self.hclk = Some(freq.into().0);
-        self
+        self.hclk = Some((freq.try_into()? as Hertz).0);
+        Ok(self)
     }
 
     /// Sets a frequency for the `APB1` bus
@@ -378,12 +380,12 @@ impl CFGR {
     ///
     /// If not manually set, it will be set to [`CFGR::sysclk`] frequency
     /// or [`CFGR::sysclk`] frequency / 2, if [`CFGR::sysclk`] > 36 Mhz
-    pub fn pclk1<F>(mut self, freq: F) -> Self
+    pub fn pclk1<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
     where
-        F: Into<Hertz>,
+        F: Rate + TryInto<Hertz<u32>>,
     {
-        self.pclk1 = Some(freq.into().0);
-        self
+        self.pclk1 = Some((freq.try_into()? as Hertz).0);
+        Ok(self)
     }
 
     /// Sets a frequency for the `APB2` bus
@@ -399,12 +401,12 @@ impl CFGR {
     ///
     ///     [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398]
     ///
-    pub fn pclk2<F>(mut self, freq: F) -> Self
+    pub fn pclk2<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
     where
-        F: Into<Hertz>,
+        F: Rate + TryInto<Hertz<u32>>,
     {
-        self.pclk2 = Some(freq.into().0);
-        self
+        self.pclk2 = Some((freq.try_into()? as Hertz).0);
+        Ok(self)
     }
 
     /// Sets the system (core) frequency
@@ -422,12 +424,12 @@ impl CFGR {
     /// even when using the internal oscillator:
     ///
     ///     [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398]
-    pub fn sysclk<F>(mut self, freq: F) -> Self
+    pub fn sysclk<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
     where
-        F: Into<Hertz>,
+        F: Rate + TryInto<Hertz<u32>>,
     {
-        self.sysclk = Some(freq.into().0);
-        self
+        self.sysclk = Some((freq.try_into()? as Hertz).0);
+        Ok(self)
     }
 
     /// Calculate the values for the pll multiplier (`PLLMUL`) and the pll divisior (`PLLDIV`).

src/spi.rs

@@ -4,7 +4,7 @@
 //!
 //! [examples/spi.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.6.0/examples/spi.rs
 
-use core::ptr;
+use core::{convert::TryInto, ptr};
 
 use crate::hal::spi::FullDuplex;
 pub use crate::hal::spi::{Mode, Phase, Polarity};
@@ -131,7 +131,7 @@ use crate::rcc::APB1;
     feature = "stm32f398"
 ))]
 use crate::rcc::APB2;
-use crate::time::rate::Hertz;
+use crate::time::rate::{Hertz, Rate};
 use core::marker::PhantomData;
 
 /// SPI error
@@ -424,9 +424,9 @@ macro_rules! hal {
                     freq: F,
                     clocks: Clocks,
                     apb2: &mut $APBX,
-                ) -> Self
+                ) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
                 where
-                    F: Into<Hertz>,
+                    F: Rate + TryInto<Hertz<u32>>,
                     SCK: SckPin<$SPIX>,
                     MISO: MisoPin<$SPIX>,
                     MOSI: MosiPin<$SPIX>,
@@ -445,6 +445,7 @@ macro_rules! hal {
                         w.ssoe().disabled()
                     });
 
+                    let freq: Hertz = freq.try_into()?;
                     // CPHA: phase
                     // CPOL: polarity
                     // MSTR: master mode
@@ -468,7 +469,7 @@ macro_rules! hal {
                             Polarity::IdleHigh => w.cpol().idle_high(),
                         };
 
-                        w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq.into()));
+                        w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq));
 
                         w.spe()
                             .enabled()
@@ -484,7 +485,7 @@ macro_rules! hal {
                             .unidirectional()
                     });
 
-                    Spi { spi, pins, _word: PhantomData }
+                    Ok(Spi { spi, pins, _word: PhantomData })
                 }
 
                 /// Releases the SPI peripheral and associated pins
@@ -494,13 +495,18 @@ macro_rules! hal {
 
                 /// Change the baud rate of the SPI
                 pub fn reclock<F>(&mut self, freq: F, clocks: Clocks)
-                    where F: Into<Hertz>
+                -> Result<(), <F as TryInto<Hertz<u32>>>::Error>
+                where
+                    F: Rate + TryInto<Hertz<u32>>,
                 {
                     self.spi.cr1.modify(|_, w| w.spe().disabled());
+
+                    let freq: Hertz = freq.try_into()?;
                     self.spi.cr1.modify(|_, w| {
-                        w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq.into()));
+                        w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq));
                         w.spe().enabled()
                     });
+                    Ok(())
                 }
 
                 fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> spi1::cr1::BR_A {