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Merge pull request #513 from stm32-rs/mpu9250
reenable mpu9250
2 parents 51321ac + 8541e29 commit ec32a32

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4 files changed

+22
-35
lines changed

4 files changed

+22
-35
lines changed

CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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### Changed
2020

21+
- Update `bxcan`, `heapless`, `mfrc522`, reenable `mpu9250` example [#513]
2122
- PWM timer auto reload value is now preloaded/buffered [#453]
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- Move from bors/manual merge to GH merge queue [#467]
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- Replace UB code by a legitimate pointer access [#480]

Cargo.toml

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ cortex-m = "0.7.6"
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cortex-m-rt = "0.7.1"
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nb = "1.1"
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embedded-dma = "0.2.0"
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bxcan = "0.7"
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bxcan = "0.8.0"
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void = { default-features = false, version = "1.0.2" }
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fugit = "0.3.7"
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fugit-timer = "0.1.3"
@@ -59,8 +59,9 @@ panic-semihosting = "0.6.0"
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panic-itm = "0.4.2"
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cortex-m-rtic = "1.1.3"
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cortex-m-semihosting = "0.5.0"
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heapless = "0.7.16"
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mfrc522 = "0.5.0"
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heapless = "0.8.0"
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mfrc522 = { version = "0.7.0", features = ["eh02"] }
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mpu9250 = "0.25.0"
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usb-device = "0.2.8"
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usbd-serial = "0.1.1"
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examples/mfrc522.rs

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Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ use panic_itm as _;
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use cortex_m::iprintln;
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use cortex_m_rt::entry;
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use mfrc522::Mfrc522;
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use mfrc522::{comm::eh02::spi::SpiInterface, Mfrc522};
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use stm32f1xx_hal::{
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pac,
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prelude::*,
@@ -44,7 +44,8 @@ fn main() -> ! {
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);
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let nss = gpioa.pa4.into_push_pull_output(&mut gpioa.crl);
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let mut mfrc522 = Mfrc522::new(spi).with_nss(nss).init().unwrap();
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let itf = SpiInterface::new(spi).with_nss(nss);
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let mut mfrc522 = Mfrc522::new(itf).init().unwrap();
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let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
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led.set_high();

examples/mpu9250.rs.disabled renamed to examples/mpu9250.rs

Lines changed: 14 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -5,27 +5,22 @@
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#![no_main]
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#![no_std]
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8-
extern crate cortex_m;
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extern crate cortex_m_rt as rt;
10-
extern crate mpu9250;
11-
extern crate panic_semihosting;
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extern crate stm32f1xx_hal as hal;
8+
use panic_halt as _;
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1410
use cortex_m::asm;
15-
use hal::delay::Delay;
16-
use hal::prelude::*;
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use hal::spi::Spi;
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use hal::stm32f103xx;
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use cortex_m_rt::entry;
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use mpu9250::Mpu9250;
20-
use rt::{entry, exception, ExceptionFrame};
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use stm32f1xx_hal as hal;
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15+
use hal::{pac, prelude::*, spi::Spi};
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#[entry]
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fn main() -> ! {
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let cp = cortex_m::Peripherals::take().unwrap();
25-
let dp = stm32f103xx::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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let mut flash = dp.FLASH.constrain();
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let mut rcc = dp.RCC.constrain();
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let rcc = dp.RCC.constrain();
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let clocks = rcc.cfgr.freeze(&mut flash.acr);
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@@ -46,36 +41,25 @@ fn main() -> ! {
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// let miso = gpiob.pb14;
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// let mosi = gpiob.pb15.into_alternate_push_pull(&mut gpiob.crh);
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49-
let spi = Spi::spi1(
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let spi = Spi::new(
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dp.SPI1,
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(sck, miso, mosi),
52-
&mut afio.mapr,
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mpu9250::MODE,
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(sck, miso, mosi, &mut afio.mapr),
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mpu9250::MODE.into(),
5448
1.MHz(),
55-
clocks,
49+
&clocks,
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);
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58-
let mut delay = Delay::new(cp.SYST, &clocks);
52+
let mut delay = cp.SYST.delay(&clocks);
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60-
let mut mpu9250 = Mpu9250::marg(spi, nss, &mut delay).unwrap();
54+
let mut mpu9250 = Mpu9250::marg_default(spi, nss, &mut delay).unwrap();
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// sanity checks
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assert_eq!(mpu9250.who_am_i().unwrap(), 0x71);
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assert_eq!(mpu9250.ak8963_who_am_i().unwrap(), 0x48);
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66-
let _a = mpu9250.all().unwrap();
60+
let _a = mpu9250.all::<[f32; 3]>().unwrap();
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6862
asm::bkpt();
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7064
loop {}
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}
72-
73-
#[exception]
74-
fn HardFault(ef: &ExceptionFrame) -> ! {
75-
panic!("{:#?}", ef);
76-
}
77-
78-
#[exception]
79-
fn DefaultHandler(irqn: i16) {
80-
panic!("Unhandled exception (IRQn = {})", irqn);
81-
}

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