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Clean up TX descriptors a little
1 parent b2fd801 commit f50db4a

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4 files changed

+12
-14
lines changed

4 files changed

+12
-14
lines changed

src/dma/raw_descriptor.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,10 @@ impl<'data, T> DescriptorRing<'data, T> {
8080
(&mut self.descriptors[index], &mut self.buffers[index])
8181
}
8282

83+
pub fn descriptors_mut(&mut self) -> impl Iterator<Item = &mut T> {
84+
self.descriptors.iter_mut()
85+
}
86+
8387
pub fn descriptors(&self) -> impl Iterator<Item = &T> {
8488
self.descriptors.iter()
8589
}
@@ -100,10 +104,6 @@ impl<'data, T> DescriptorRing<'data, T> {
100104
&self.buffers[self.buffers.len() - 1]
101105
}
102106

103-
pub fn descriptors_mut(&mut self) -> impl Iterator<Item = &mut T> {
104-
self.descriptors.iter_mut()
105-
}
106-
107107
pub fn descriptors_and_buffers(
108108
&mut self,
109109
) -> impl Iterator<Item = (&mut T, &mut [u8; MTU + 2])> {

src/dma/tx/f_series_desc.rs

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -65,8 +65,9 @@ impl TxDescriptor {
6565
}
6666
}
6767

68-
pub(super) fn setup(&mut self, buffer: &mut [u8]) {
69-
self.set_buffer(buffer);
68+
pub(super) fn setup(&mut self) {
69+
(0..crate::dma::raw_descriptor::DESC_SIZE)
70+
.for_each(|i| unsafe { self.inner_raw.write(i, 0) });
7071
}
7172

7273
#[allow(unused)]

src/dma/tx/h_desc.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -149,10 +149,10 @@ impl TxDescriptor {
149149
(self.inner_raw.read(3) & TXDESC_3_LD) == TXDESC_3_LD
150150
}
151151

152-
// Placeholder for API parity with f-series descriptor.
153-
pub(super) fn setup(&mut self, _: &[u8]) {
152+
pub(super) fn setup(&mut self) {
154153
// Zero-out all fields in the descriptor
155154
(0..4).for_each(|n| unsafe { self.inner_raw.write(n, 0) });
155+
self.packet_id.take();
156156
}
157157

158158
pub(super) fn is_owned(&self) -> bool {

src/dma/tx/mod.rs

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -95,8 +95,8 @@ impl<'data> TxRing<'data, NotRunning> {
9595
/// Start the Tx DMA engine
9696
pub fn start(mut self, eth_dma: &ETHERNET_DMA) -> TxRing<'data, Running> {
9797
// Setup ring
98-
for (descriptor, buffer) in self.ring.descriptors_and_buffers() {
99-
descriptor.setup(buffer);
98+
for descriptor in self.ring.descriptors_mut() {
99+
descriptor.setup();
100100
}
101101

102102
#[cfg(feature = "f-series")]
@@ -120,10 +120,7 @@ impl<'data> TxRing<'data, NotRunning> {
120120

121121
// Assert that the descriptors are properly aligned.
122122
assert!(ring_ptr as u32 & !0b11 == ring_ptr as u32);
123-
assert!(
124-
self.ring.last_descriptor() as *const _ as u32 & !0b11
125-
== self.ring.last_descriptor() as *const _ as u32
126-
);
123+
assert!(self.ring.last_descriptor() as *const _ as u32 % 4 == 0);
127124

128125
// Set the start pointer.
129126
eth_dma

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