Make hclk/sysclk divisible with 8

datdenkikniet · datdenkikniet · commit b2fd80193650 · 2023-02-08T23:09:12.000+01:00
diff --git a/examples/common.rs b/examples/common.rs
@@ -71,7 +71,7 @@ pub fn setup_peripherals(p: stm32_eth::stm32::Peripherals) -> (Clocks, Gpio, Par
     {
         let rcc = p.RCC.constrain();
 
-        let clocks = rcc.cfgr.sysclk(100.MHz()).hclk(100.MHz());
+        let clocks = rcc.cfgr.sysclk(96.MHz()).hclk(96.MHz());
 
         #[cfg(feature = "stm32f4xx-hal")]
         let clocks = {

Original file line number	Diff line number	Diff line change
`@@ -71,7 +71,7 @@ pub fn setup_peripherals(p: stm32_eth::stm32::Peripherals) -> (Clocks, Gpio, Par`
`71`	`71`	`{`
`72`	`72`	`let rcc = p.RCC.constrain();`
`73`	`73`
`74`		`- let clocks = rcc.cfgr.sysclk(100.MHz()).hclk(100.MHz());`
	`74`	`+ let clocks = rcc.cfgr.sysclk(96.MHz()).hclk(96.MHz());`
`75`	`75`
`76`	`76`	`#[cfg(feature = "stm32f4xx-hal")]`
`77`	`77`	`let clocks = {`