Fix CIC bits in TX descriptor & enable more interrupts

Author: datdenkikniet

src/dma/mod.rs

@@ -257,6 +257,15 @@ impl<'rx, 'tx> EthernetDMA<'rx, 'tx> {
                 // Transmit Interrupt Enable
                 .tie()
                 .set_bit()
+                // Abnormal Interrupt Summary enable
+                .aie()
+                .set_bit()
+                // Receive Buffer Unavailable
+                .rbue()
+                .set_bit()
+                // Transmit Buffer Unavailable
+                .tbue()
+                .set_bit()
         });
 
         // Enable ethernet interrupts
@@ -429,6 +438,10 @@ fn eth_interrupt_handler_impl(eth_dma: &ETHERNET_DMA) -> InterruptReasonSummary
                 .set_bit()
                 .ri()
                 .set_bit()
+                .rbu()
+                .set_bit()
+                .tbu()
+                .set_bit()
         });
 
         (

src/dma/rx/h_desc.rs

@@ -55,16 +55,16 @@ mod consts {
     pub const RXDESC_3_LT_MASK: u32 = 0b111 << RXDESC_3_LT_SHIFT;
     /// Length/Type Field
     #[allow(non_camel_case_types)]
-    #[repr(u8)]
+    #[repr(u32)]
     pub enum RXDESC_3_LT {
-        Length = 0b000,
-        Type = 0b001,
-        Reserved = 0b010,
-        ArpRequest = 0b011,
-        TypeWithVlan = 0b100,
-        TypeWIthDoubleVlan = 0b101,
-        MacControl = 0b110,
-        Oam = 0b111,
+        Length = 0b000 << RXDESC_3_LT_SHIFT,
+        Type = 0b001 << RXDESC_3_LT_SHIFT,
+        Reserved = 0b010 << RXDESC_3_LT_SHIFT,
+        ArpRequest = 0b011 << RXDESC_3_LT_SHIFT,
+        TypeWithVlan = 0b100 << RXDESC_3_LT_SHIFT,
+        TypeWIthDoubleVlan = 0b101 << RXDESC_3_LT_SHIFT,
+        MacControl = 0b110 << RXDESC_3_LT_SHIFT,
+        Oam = 0b111 << RXDESC_3_LT_SHIFT,
     }
 
     /// Error Summary
@@ -162,10 +162,6 @@ impl RxDescriptor {
                 .modify(3, |w| w | RXDESC_3_OWN | RXDESC_3_IOC);
         }
 
-        cortex_m::asm::dsb();
-
-        assert!(self.is_owned());
-
         // Used to flush the store buffer as fast as possible to make the buffer available for the
         // DMA.
         #[cfg(feature = "fence")]

src/dma/rx/mod.rs

@@ -216,6 +216,7 @@ impl<'data> RxRing<'data, Running> {
 
         let entry = self.next_entry;
         let entries_len = self.ring.len();
+
         let (descriptor, buffer) = self.ring.get(entry);
 
         let mut res = descriptor.take_received(packet_id, buffer);
@@ -226,20 +227,18 @@ impl<'data> RxRing<'data, Running> {
 
         #[cfg(all(feature = "ptp", feature = "stm32h7xx-hal"))]
         let (timestamp, descriptor, buffer) = {
-            if res.as_mut().err() != Some(&mut RxError::WouldBlock) {
+            if res.is_ok() {
                 let desc_has_timestamp = descriptor.has_timestamp();
 
                 drop(descriptor);
                 drop(buffer);
 
                 // On H7's, the timestamp is stored in the next Context
                 // descriptor.
+                let (ctx_descriptor, ctx_des_buffer) = self.ring.get(self.next_entry);
+
                 let timestamp = if desc_has_timestamp {
-                    let (ctx_descriptor, ctx_des_buffer) = self.ring.get(self.next_entry);
                     if let Some(timestamp) = ctx_descriptor.read_timestamp() {
-                        ctx_descriptor.set_owned(ctx_des_buffer);
-                        // Advance over this buffer
-                        self.next_entry = (self.next_entry + 1) % entries_len;
                         Some(timestamp)
                     } else {
                         None
@@ -248,6 +247,12 @@ impl<'data> RxRing<'data, Running> {
                     None
                 };
 
+                if !ctx_descriptor.is_owned() {
+                    // Advance over this buffer
+                    self.next_entry = (self.next_entry + 1) % entries_len;
+                    ctx_descriptor.set_owned(&ctx_des_buffer);
+                }
+
                 let (descriptor, buffer) = self.ring.get(entry);
 
                 descriptor.attach_timestamp(timestamp);

src/dma/tx/h_desc.rs

@@ -68,10 +68,10 @@ mod consts {
     #[repr(u32)]
     #[allow(non_camel_case_types)]
     pub enum TXDESC_3_CIC {
-        Disabled = 0b00,
-        IpHeaderOnly = 0b01,
-        IpHeaderAndPayloadOnly = 0b10,
-        IpHeaderAndPayloadAndPseudoHeader = 0b11,
+        Disabled = 0b00 << TXDESC_3_CIC_SHIFT,
+        IpHeaderOnly = 0b01 << TXDESC_3_CIC_SHIFT,
+        IpHeaderAndPayloadOnly = 0b10 << TXDESC_3_CIC_SHIFT,
+        IpHeaderAndPayloadAndPseudoHeader = 0b11 << TXDESC_3_CIC_SHIFT,
     }
     /// Checksum Insertion Control mask
     pub const TXDESC_3_CIC_MASK: u32 = 0b11 << TXDESC_3_CIC_SHIFT;
@@ -192,7 +192,7 @@ impl TxDescriptor {
 
             self.inner_raw.modify(3, |w| {
                 w | TXDESC_3_OWN
-                    | TXDESC_3_CIC::IpHeaderAndPayloadOnly as u32
+                    | TXDESC_3_CIC::IpHeaderAndPayloadAndPseudoHeader as u32
                     | TXDESC_3_FD
                     | TXDESC_3_LD
                     | tx_len