Add ability to configure PPS pin

Author: Johannes Cornelis Draaijer

examples/arp.rs

@@ -41,7 +41,7 @@ fn main() -> ! {
 
     defmt::info!("Enabling ethernet...");
 
-    let (eth_pins, mdio, mdc) = common::setup_pins(gpio);
+    let (eth_pins, mdio, mdc, _) = common::setup_pins(gpio);
 
     let mut rx_ring: [RxRingEntry; 2] = Default::default();
     let mut tx_ring: [TxRingEntry; 2] = Default::default();

examples/common.rs

@@ -133,12 +133,19 @@ mod pins {
     pub type Mdio = PA2<Alternate<11>>;
     pub type Mdc = PC1<Alternate<11>>;
 
+    #[cfg(not(pps = "alternate"))]
+    pub type Pps = PB5<Output<PushPull>>;
+
+    #[cfg(pps = "alternate")]
+    pub type Pps = PG8<Output<PushPull>>;
+
     pub fn setup_pins(
         gpio: Gpio,
     ) -> (
         EthPins<RefClk, Crs, TxEn, TxD0, TxD1, RxD0, RxD1>,
         Mdio,
         Mdc,
+        Pps,
     ) {
         #[allow(unused_variables)]
         let Gpio {
@@ -183,6 +190,11 @@ mod pins {
             gpioc.pc1.into_alternate().set_speed(Speed::VeryHigh),
         );
 
+        #[cfg(not(pps = "alternate"))]
+        let pps = gpiob.pb5.into_push_pull_output();
+        #[cfg(pps = "alternate")]
+        let pps = gpiog.pg8.into_push_pull_output();
+
         (
             EthPins {
                 ref_clk,
@@ -195,6 +207,7 @@ mod pins {
             },
             mdio,
             mdc,
+            pps,
         )
     }
 }
@@ -223,12 +236,15 @@ mod pins {
     pub type Mdio = PA2<Alternate<PushPull>>;
     pub type Mdc = PC1<Alternate<PushPull>>;
 
+    pub type Pps = PB5<Output<PushPull>>;
+
     pub fn setup_pins(
         gpio: Gpio,
     ) -> (
         EthPins<RefClk, Crs, TxEn, TxD0, TxD1, RxD0, RxD1>,
         Mdio,
         Mdc,
+        Pps,
     ) {
         let Gpio {
             mut gpioa,
@@ -248,6 +264,8 @@ mod pins {
         let tx_d0 = gpiob.pb12.into_alternate_push_pull(&mut gpiob.crh);
         let tx_d1 = gpiob.pb13.into_alternate_push_pull(&mut gpiob.crh);
 
+        let pps = gpiob.pb5.into_push_pull_output(&mut gpiob.crl);
+
         let pins = EthPins {
             ref_clk,
             crs,
@@ -258,7 +276,7 @@ mod pins {
             rx_d1,
         };
 
-        (pins, mdio, mdc)
+        (pins, mdio, mdc, pps)
     }
 }
 

examples/ip.rs

@@ -43,7 +43,7 @@ fn main() -> ! {
 
     defmt::info!("Enabling ethernet...");
 
-    let (eth_pins, _mdio, _mdc) = common::setup_pins(gpio);
+    let (eth_pins, _mdio, _mdc, _) = common::setup_pins(gpio);
 
     let mut rx_ring: [RxRingEntry; 2] = Default::default();
     let mut tx_ring: [TxRingEntry; 2] = Default::default();

examples/pktgen.rs

@@ -40,7 +40,7 @@ fn main() -> ! {
     setup_systick(&mut cp.SYST);
 
     defmt::info!("Enabling ethernet...");
-    let (eth_pins, mdio, mdc) = common::setup_pins(gpio);
+    let (eth_pins, mdio, mdc, _) = common::setup_pins(gpio);
 
     let mut rx_ring: [RxRingEntry; 2] = Default::default();
     let mut tx_ring: [TxRingEntry; 2] = Default::default();

examples/rtic-echo.rs

@@ -78,7 +78,7 @@ mod app {
         let mono = Systick::new(core.SYST, clocks.hclk().raw());
 
         defmt::info!("Setting up pins");
-        let (pins, mdio, mdc) = crate::common::setup_pins(gpio);
+        let (pins, mdio, mdc, _) = crate::common::setup_pins(gpio);
 
         defmt::info!("Configuring ethernet");
 

examples/rtic-timestamp.rs

@@ -79,13 +79,15 @@ mod app {
         let mono = Systick::new(core.SYST, clocks.hclk().raw());
 
         defmt::info!("Setting up pins");
-        let (pins, mdio, mdc) = crate::common::setup_pins(gpio);
+        let (pins, mdio, mdc, pps) = crate::common::setup_pins(gpio);
 
         defmt::info!("Configuring ethernet");
 
-        let Parts { dma, mac, ptp } =
+        let Parts { dma, mac, mut ptp } =
             stm32_eth::new_with_mii(ethernet, rx_ring, tx_ring, clocks, pins, mdio, mdc).unwrap();
 
+        ptp.enable_pps(pps);
+
         defmt::info!("Enabling interrupts");
         dma.enable_interrupt();
 

src/ptp/mod.rs

@@ -10,6 +10,9 @@ pub use timestamp::Timestamp;
 mod subseconds;
 pub use subseconds::{Subseconds, NANOS_PER_SECOND, SUBSECONDS_PER_SECOND, SUBSECONDS_TO_SECONDS};
 
+mod pps_pin;
+pub use pps_pin::PPSPin;
+
 /// Access to the IEEE 1508v2 PTP peripheral present on the ethernet peripheral.
 ///
 /// On STM32FXXX's, the PTP peripheral has/uses the following important parts:
@@ -191,6 +194,14 @@ impl EthernetPTP {
             }
         }
     }
+
+    /// Enable the PPS output on the provided pin.
+    pub fn enable_pps<P>(&mut self, pin: P) -> P::Output
+    where
+        P: PPSPin,
+    {
+        pin.enable()
+    }
 }
 
 /// Setting and configuring target time interrupts on the STM32F107 does not
@@ -230,6 +241,22 @@ impl EthernetPTP {
         }
         is_tsint
     }
+
+    /// Configure the PPS output frequency.
+    ///
+    /// The PPS output frequency becomes `2 ^ pps_freq`. `pps_freq` is
+    /// clamped to `[0..31]`.
+    pub fn set_pps_freq(&mut self, pps_freq: u8) {
+        let pps_freq = pps_freq.max(31);
+
+        // SAFETY: we atomically write to the PTPPPSCR register, which is
+        // not read or written to anywhere else. The SVD files are incorrectly
+        // saying that the bits in this register are read-only.
+        unsafe {
+            let ptpppscr = self.eth_ptp.ptpppscr.as_ptr() as *mut u32;
+            core::ptr::write_volatile(ptpppscr, pps_freq as u32);
+        }
+    }
 }
 
 #[cfg(all(test, not(target_os = "none")))]

src/ptp/pps_pin.rs

@@ -0,0 +1,65 @@
+/// Pins that can be used as PPS output
+///
+/// SAFETY: only pins that are capable of being a PPS output according
+/// to the datasheets of respective parts may implement this trait.
+pub unsafe trait PPSPin {
+    /// The output type of this pin, in which it acts as a PPS output.
+    type Output;
+
+    /// Enable the PPS output.
+    fn enable(self) -> Self::Output;
+}
+
+#[allow(unused_macros)]
+macro_rules! impl_pps_pin {
+    ($([$name:ty, $output:ty]),*) => {
+        $(
+            unsafe impl super::PPSPin for $name {
+                type Output = $output;
+
+                fn enable(self) -> Self::Output {
+                    self.into_alternate()
+                }
+            }
+        )*
+    };
+}
+
+#[cfg(feature = "stm32f4xx-hal")]
+mod impl_pps_pin {
+    use crate::hal::gpio::{Alternate, Output, PushPull, PB5, PG8};
+
+    impl_pps_pin!([PG8<Output<PushPull>>, PG8<Alternate<11>>], [PB5<Output<PushPull>>, PB5<Alternate<11>>]);
+}
+
+#[cfg(feature = "stm32f7xx-hal")]
+mod impl_pps_pin {
+    use crate::hal::gpio::{Alternate, Output, PushPull, PB5, PG8};
+
+    impl_pps_pin!([PG8<Output<PushPull>>, PG8<Alternate<11>>], [PB5<Output<PushPull>>, PB5<Alternate<11>>]);
+}
+
+#[cfg(feature = "stm32f1xx-hal")]
+mod impl_pps_pin {
+    use crate::hal::gpio::{Alternate, Output, PushPull, PB5};
+
+    unsafe impl super::PPSPin for PB5<Output<PushPull>> {
+        type Output = PB5<Alternate<PushPull>>;
+
+        fn enable(self) -> Self::Output {
+            // Within this critical section, modifying the `CRL` register can
+            // only be unsound if this critical section preempts other code
+            // that is modifying the same register
+            cortex_m::interrupt::free(|_| {
+                // SAFETY: this is sound as long as the API of the HAL and structure of the CRL
+                // struct does not change. In case the size of the `CRL` struct is changed, compilation
+                // will fail as `mem::transmute` can only convert between types of the same size.
+                //
+                // This guards us from unsound behaviour introduced by point releases of the f1 hal
+                let cr: &mut _ = &mut unsafe { core::mem::transmute(()) };
+                // The speed can only be changed on output pins
+                self.into_alternate_push_pull(cr)
+            })
+        }
+    }
+}

src/setup.rs

@@ -305,10 +305,7 @@ macro_rules! impl_pins {
     };
 }
 
-#[cfg(all(
-    feature = "device-selected",
-    any(feature = "stm32f4xx-hal", feature = "stm32f7xx-hal")
-))]
+#[cfg(any(feature = "stm32f4xx-hal", feature = "stm32f7xx-hal"))]
 impl_pins!(
     RmiiRefClk: [
         PA1<Input>,