Enable enhanced descriptors to support checksums

Author: dsgruss

src/desc.rs

@@ -5,7 +5,7 @@ use volatile_register::{RO, RW};
 
 #[repr(C)]
 pub struct Descriptor {
-    desc: Aligned<A8, [u32; 4]>,
+    desc: Aligned<A8, [u32; 8]>,
 }
 
 impl Clone for Descriptor {
@@ -25,7 +25,7 @@ impl Default for Descriptor {
 impl Descriptor {
     pub const fn new() -> Self {
         Self {
-            desc: Aligned([0; 4]),
+            desc: Aligned([0; 8]),
         }
     }
 

src/lib.rs

@@ -240,7 +240,12 @@ pub unsafe fn new_unchecked<'rx, 'tx>(
     eth_mmc.mmctimr.modify(|r, w| w.bits(r.bits() | (1 << 21)));
 
     // bus mode register
-    eth_dma.dmabmr.modify(|_, w|
+    eth_dma.dmabmr.modify(|_, w| {
+        // For any non-f107 chips, we must use enhanced descriptor format to support checksum
+        // offloading and/or timestamps.
+        #[cfg(not(feature = "stm32f107"))]
+        let w = w.edfe().set_bit();
+
         // Address-aligned beats
         w.aab()
             .set_bit()
@@ -258,7 +263,8 @@ pub unsafe fn new_unchecked<'rx, 'tx>(
             .bits(0b01)
             // Use separate PBL
             .usp()
-            .set_bit());
+            .set_bit()
+    });
 
     let mut dma = EthernetDMA {
         eth_dma,