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Add checksum insertion and offloading
1 parent ae3a846 commit f3ff7fb

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3 files changed

+17
-3
lines changed

3 files changed

+17
-3
lines changed

src/lib.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,9 @@ pub unsafe fn new_unchecked<'rx, 'tx>(
175175
// Duplex mode
176176
.dm()
177177
.set_bit()
178+
// IPv4 checksum offload
179+
.ipco()
180+
.set_bit()
178181
// Automatic pad/CRC stripping
179182
.apcs()
180183
.set_bit()

src/smoltcp_phy.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
use crate::{rx::RxPacket, tx::TxError, EthernetDMA};
22
use core::intrinsics::transmute;
3-
use smoltcp::phy::{Device, DeviceCapabilities, RxToken, TxToken};
3+
use smoltcp::phy::{ChecksumCapabilities, Device, DeviceCapabilities, RxToken, TxToken};
44
use smoltcp::time::Instant;
55
use smoltcp::Error;
66

@@ -13,6 +13,7 @@ impl<'a, 'rx, 'tx, 'b> Device<'a> for &'b mut EthernetDMA<'rx, 'tx> {
1313
let mut caps = DeviceCapabilities::default();
1414
caps.max_transmission_unit = super::MTU;
1515
caps.max_burst_size = Some(1);
16+
caps.checksum = ChecksumCapabilities::ignored();
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caps
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}
1819

src/tx.rs

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,9 @@ const TXDESC_0_IC: u32 = 1 << 30;
1818
const TXDESC_0_FS: u32 = 1 << 28;
1919
/// Last segment of frame
2020
const TXDESC_0_LS: u32 = 1 << 29;
21+
/// Checksum insertion control
22+
const TXDESC_0_CIC0: u32 = 1 << 23;
23+
const TXDESC_0_CIC1: u32 = 1 << 22;
2124
/// Transmit end of ring
2225
const TXDESC_0_TER: u32 = 1 << 21;
2326
/// Second address chained
@@ -115,8 +118,15 @@ impl RingDescriptor for TxDescriptor {
115118
fn setup(&mut self, buffer: *const u8, _len: usize, next: Option<&Self>) {
116119
// Defer this initialization to this function, so we can have `RingEntry` on bss.
117120
unsafe {
118-
self.desc
119-
.write(0, TXDESC_0_TCH | TXDESC_0_IC | TXDESC_0_FS | TXDESC_0_LS);
121+
self.desc.write(
122+
0,
123+
TXDESC_0_TCH
124+
| TXDESC_0_IC
125+
| TXDESC_0_FS
126+
| TXDESC_0_LS
127+
| TXDESC_0_CIC0
128+
| TXDESC_0_CIC1,
129+
);
120130
}
121131
self.set_buffer1(buffer);
122132
match next {

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