Merge pull request #48 from dsgruss/master

Add checksum insertion and offloading

Author: datdenkikniet

src/desc.rs

@@ -3,9 +3,15 @@ use core::ops::{Deref, DerefMut};
 use aligned::{Aligned, A8};
 use volatile_register::{RO, RW};
 
+#[cfg(not(feature = "stm32f107"))]
+const DESC_SIZE: usize = 8;
+
+#[cfg(feature = "stm32f107")]
+const DESC_SIZE: usize = 4;
+
 #[repr(C)]
 pub struct Descriptor {
-    desc: Aligned<A8, [u32; 4]>,
+    desc: Aligned<A8, [u32; DESC_SIZE]>,
 }
 
 impl Clone for Descriptor {
@@ -25,7 +31,7 @@ impl Default for Descriptor {
 impl Descriptor {
     pub const fn new() -> Self {
         Self {
-            desc: Aligned([0; 4]),
+            desc: Aligned([0; DESC_SIZE]),
         }
     }
 

src/lib.rs

@@ -175,6 +175,9 @@ pub unsafe fn new_unchecked<'rx, 'tx>(
             // Duplex mode
             .dm()
             .set_bit()
+            // IPv4 checksum offload
+            .ipco()
+            .set_bit()
             // Automatic pad/CRC stripping
             .apcs()
             .set_bit()
@@ -237,7 +240,12 @@ pub unsafe fn new_unchecked<'rx, 'tx>(
     eth_mmc.mmctimr.modify(|r, w| w.bits(r.bits() | (1 << 21)));
 
     // bus mode register
-    eth_dma.dmabmr.modify(|_, w|
+    eth_dma.dmabmr.modify(|_, w| {
+        // For any non-f107 chips, we must use enhanced descriptor format to support checksum
+        // offloading and/or timestamps.
+        #[cfg(not(feature = "stm32f107"))]
+        let w = w.edfe().set_bit();
+
         // Address-aligned beats
         w.aab()
             .set_bit()
@@ -255,7 +263,8 @@ pub unsafe fn new_unchecked<'rx, 'tx>(
             .bits(0b01)
             // Use separate PBL
             .usp()
-            .set_bit());
+            .set_bit()
+    });
 
     let mut dma = EthernetDMA {
         eth_dma,

src/smoltcp_phy.rs

@@ -1,6 +1,6 @@
 use crate::{rx::RxPacket, tx::TxError, EthernetDMA};
 use core::intrinsics::transmute;
-use smoltcp::phy::{Device, DeviceCapabilities, RxToken, TxToken};
+use smoltcp::phy::{ChecksumCapabilities, Device, DeviceCapabilities, RxToken, TxToken};
 use smoltcp::time::Instant;
 use smoltcp::Error;
 
@@ -13,6 +13,7 @@ impl<'a, 'rx, 'tx, 'b> Device<'a> for &'b mut EthernetDMA<'rx, 'tx> {
         let mut caps = DeviceCapabilities::default();
         caps.max_transmission_unit = super::MTU;
         caps.max_burst_size = Some(1);
+        caps.checksum = ChecksumCapabilities::ignored();
         caps
     }
 

src/tx.rs

@@ -18,6 +18,9 @@ const TXDESC_0_IC: u32 = 1 << 30;
 const TXDESC_0_FS: u32 = 1 << 28;
 /// Last segment of frame
 const TXDESC_0_LS: u32 = 1 << 29;
+/// Checksum insertion control
+const TXDESC_0_CIC0: u32 = 1 << 23;
+const TXDESC_0_CIC1: u32 = 1 << 22;
 /// Transmit end of ring
 const TXDESC_0_TER: u32 = 1 << 21;
 /// Second address chained
@@ -115,8 +118,15 @@ impl RingDescriptor for TxDescriptor {
     fn setup(&mut self, buffer: *const u8, _len: usize, next: Option<&Self>) {
         // Defer this initialization to this function, so we can have `RingEntry` on bss.
         unsafe {
-            self.desc
-                .write(0, TXDESC_0_TCH | TXDESC_0_IC | TXDESC_0_FS | TXDESC_0_LS);
+            self.desc.write(
+                0,
+                TXDESC_0_TCH
+                    | TXDESC_0_IC
+                    | TXDESC_0_FS
+                    | TXDESC_0_LS
+                    | TXDESC_0_CIC0
+                    | TXDESC_0_CIC1,
+            );
         }
         self.set_buffer1(buffer);
         match next {