verilog-uart

UART loopback using Verilog.

Lattice ice40 HX1K FPGA

Tools: VS Code with Verilog-HDL/SystemVerilog/Bluespec SystemVerilog exntension (Extension ID: mshr-h.veriloghdl)

iceCube2

Diamond Programmer

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Binary_To_Seven_Segment.v		Binary_To_Seven_Segment.v
Debounce_Project_Top.v		Debounce_Project_Top.v
Debounce_Switch.v		Debounce_Switch.v
Led_Blinking.v		Led_Blinking.v
Led_Blinking_Top.v		Led_Blinking_Top.v
README.md		README.md
UART_Loopback_Top.v		UART_Loopback_Top.v
UART_RX.v		UART_RX.v
UART_RX_Top.v		UART_RX_Top.v
UART_TX.v		UART_TX.v

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