LaunchLab-Freshers-Training

This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK design.

Some Useful Videos on IC Design

• PROCESSING TECHNOLOGY
  • Wafer Manufacturing Process
  • Making Memory Chips -- Processing steps -- Micron Technology
  • Chip Manufacturing Process -- How are chips made -- Infeneon
  • VLSI Fabrication Process
  • Photolithography -- Step by Step
  • VLSI - Lecture 2b: The Manufacturing Process - Detailed Process Flow
• MOSFET MECHANICS
  • How MOSFETs and Field-Effect Transistors Work
  • How Transistors Work - The MOSFET
  • MOSFET: Physical View
  • MOSFET Working animation
  • What is a CMOS?
• NAND FLASH MEMORY
  • What's 3D NAND and 2D NAND Flash Memory

Course Contents

Week-1: Pre-requisites

• Fundamentals of RC Circuits: Test your understanding by solving assignments. Test: RC Circuits
• Fundamentals of Digital Logic: Test your understanding by solving assignments. Test: Digital Logic Design
  • Reference Book: Digital Logic and Computer Design by M. Morris Mano. [Link]
• Fundamentals of Electrical Circuits: Test your understanding by solving assignments. Test: Electrical Circuits
  • Reference Book: Fundamentals of Electrical Circuits by Alexander and Sadiku. [Link]
• Fundamentals of Semiconductor Devices: Test your understanding by solving assignments. Test: Semiconductor Devices
• Fundamentas of UNIX:
  • Practicing basic UNIX commands. [Link]
  • Practicing frequently used and advanced UNIX commands. [Link]
  • Practicing file editing commands. [Link]
  • Test your understanding by solving assignments. Test: comming soon

Week-2: Introduction to Digital Logic Circuit Design (Gate Level)

• Logic Gates: Understanding of basic (NOT, AND, OR), universal (NAND, NOR) and special logic gates (X-OR,X-NOR).
• Truth Table & K-Map: Draw the truth table and find out the logic circuit using K-Map (up to 5 variable).
• Combinational Circuit: Draw the following circuits: Adders, Subtractors, Multiplexers, De-multiplexers, Decoders, Encoders and Code converters.
• Sequential Circuits: Draw the following circuits: Latches, Flip-Flops, Resisters, Counters and FSM.
  • Understanding the concept of setup time. hold time, removal time, recovery time etc.
• Misc.: Multiplexer and Decoder based logic circuit design, Edge detector circuit design.
• Logic States: Understanding the loging states and their relevances: 1, 0, X, Z.
• Timing Diagram: Understanding the timing diagram of all the combi and sequential logic circuits.
• Reference Book: Digital Logic and Computer Design by M. Morris Mano. [Link]

Week-3: Basics of CMOS VLSI Design

• Introduction: Fundamentals of VLSI Design and overview of Sand-to-Silicon.
• IC Design Flow: Overview of Digital and Custom IC Design Flow and requirement of Computer Aided Design (CAD) Tools and Process Design Kit (PDK).
  • Digital IC Flow: Spec --> RTL --> RTL Verification --> Gate-level synthesis --> Gate-level simulation --> Physical Design --> Physical Verification --> parasitic extraction --> Post-layout verification.
  • Custom IC Flow (Analog IC Design): Spec --> Circuit Design --> Circuit Simulation --> Layout Design --> Layout Verification --> Parasitic Extraction --> Post-layout Simulation. [Notes]
  • Requirements of the different CAD tools and PDK in different phase of the IC Design Flow. [Notes]
• IC manufacturing process: [Link]
  • Difference between Sub-micron, deep sub-micron and ultra-deep sub-micron process.
  • Detailed understanding of sub-micron process.
  • Passive IC devices and its fabrication: Resistor and Capacitor
  • MOSFET and CMOS Inverter fabrication process, cross-sectional view, top view and 3D view.

Week-4: Fundamentals of MOSFET

• MOS Structure: Understanding of Metal-Oxide-Semiconductor structure || understanding of accumulation, depletion and inverssion region of operation || understanding of Q-V and C-V characteristics of MOS structure.
  • MOS Stucture-1 [Notes] || [Video]
  • MOS Stucture-2 [Notes] || [Video]
  • MOS Stucture-3 [Notes] || [Video]
  • Assignment: Assignment-1: MOS-Structure
• MOSFET: Understanding of Metal-Oxide-Field-Effect-Transistor (MOSFET), working principle, regions of operation, Id-Vgs and Id-Vds characteristics, Body effects, Channel length modulations and intrinisic capacitances.
  • Metal Oxide Semiconductor Field Effect Transistor-1 [Notes] || [Video]
  • Metal Oxide Semiconductor Field Effect Transistor-2 [Notes] || [Video]
• MOSFET Capacitance: Understanding of different intrinsic capacitances (overlap capacitance, channel capacitance, junction capacitance) of a MOSFET
  • MOSFET Capacitance [Notes] || [Video]
• Short Channel Effects: Understanding of MOSFET scaling and differenct short channel effects: Drain induced barrier lowering (DIBL), Velocity Saturation, Mobility degradaton, Hot carrier effects and Impact ionisation.
  • Short Channel Effects [Notes]
• Asignment: Assignment-2: MOSFET with Capacitor

Week-5: Circuit Simulaton using CAD tools

• Circuit Simulation Understanding of schematic drawing, SPICE net-list, model file and circuit simulation.
• Simulation Types Different type of Simulations: Operating point, DC, Transient and AC.
  • Schematic Drawing and Symbol Creation
  • DC Simulation
  • Transient Simulation
• MOSFET Characterization: Simple circuit design using NMOSFET and PMOSFET to characterize Id-Vgs and Id-Vds curves with PVT variations.
• Parameter Extraction: Extraction of the simple level-1 parameters (VT0, KP, LAMDA, GAMMA, PHI) from the curve and comparing the results using Level-1 model and BSIM model.
• PVT Variation: Understanding of Process, Voltage and Temperature (PVT) variation
• Sensitivity and mismatch analysis: Understanding the random variation and mismatch analysis by Monte Carlo simulations.
• Parametric simulation: Parametric analysis and circuit simulation using ADE-XL

Week-6: CMOS Inverter Design

• CMOS inverter: Understanding of CMOS inverter design, CMOS advantages, static characteristics, dynamic characteristics, power and energy consumptions.
  • Static Characteristics [Notes] || [Video]
  • Switching Characteristics and Delay Calculation [Notes] || [Video]
  • Static and Dynamic Power Dissipation [Notes] || [Video]
• Interconnect Parasitics: Understanding the wiring capacitance: parallel plate capacitance, coupling capacitance, fringing capacitance and different capacitance models.
  • Interconnect Parasitics [Notes] || [Video]
• Inverter Chain: Understanding of Inverter chain design to drive a higher capacitive load || Understanding of number of stages ans stage ratio || Understanding of optimal delay.
  • Inverter Chain Design [Notes] || [Video]
• Design and Simulation: Design, simulation and charactrization all of the above.

Week-7: Other Combinational and Sequential Circuit Design

• Other Combi: Design other combinational logics like, NAND gate, NOR gate, MUX and transmission gates.
  • *CMOS Logic Circuits & Complex Logic Circuits [Notes] || [Video]
  • CMOS Transmission Gate [Notes] || [Video]
  • Pseudo NMOS Logic [Notes] || [Video]
• Sequential Logic Circuits: Understanding of latch and flip-flop design || understanding of setup, hold and propagation time
  • Latch and Flip-Flop Circuits [Notes] || [Video]
  • Sequential Logic Circuits [Slides] || [Video]
  • Setup, Hold and Propagation delay of D-FF [Notes] || [Video]
  • Hold Time Analysis of D-FF [] || [Video]
• Static Timing Analysis (STA) [Slides] || [Notes]
  • Delays, timing arc, timing paths, setup and hold constraints, setup and hold time violations, recovery and remova time and its violations
• Assignments: Assignment-1

Week-8: Layout Design

• Layout Basics: Layer details (Metal, poly, diffusion, OD, N-Well, P-substrate, P+ Diff, N+ Diff, Via, Contact, Ports and Lable etc) || Layer drawing, layer interacting and, port and label creating || Layout Design of NMOS and PMOS
• Layout Design of Inverter: Undestanding of Design Rule Check (DRC) || Understanding of Layout Vs Schematic (LVS) || Understanding of Parasic Extraction (PEX) || Understanding of Post Layout Simulation (PLS)
• Other Layouts: Layout Design of NAND and NOR Gates || Layout Design of Resistors, Capacitors and BJTs
• DRC, LVS and PEX in details: DRC Rule deck file and different rules || LVS rule deck file || PEX rule deck file || Basics of P-Cell
• Asignment and aassessment:

Session Activities

• [Nov-8] Introduction to CMOS VLSI Design Flow [Video]
  • [Suggested Reading]: [Hodges] Chapter-1, [Kang] Chapter-1
• [Nov-9] Introduction to CMOS PRocessing [Video]
  • [Suggested Reading]: [Hodges] Section 3.1,3.2
  • [Suggested Problems]: [Hodges] Prob 3.11, 3.12
• [Nov-10] Session-1: Passive Integrated Circuit Devices. Session-2: MOS Device-I: Threshold Voltage [Video:Session-1 | Video:Session-2]
  • [Suggested Reading]: [Hodges] Section 3.2.4, 3.2.5
  • [Suggested Problems]: [Hodges] Example 3.1, Prob 3.13, 3.14
• [Nov-11] Session-1: MOS Device-II: IV Characteristics and MOS Capacitance. Session-2: Basic Circuits. [Video:Session-1 | Video:Session-2]
  • [Suggested Reading]: [Hodges] Section 2.2.1, 2.2.2, 2.2.3, 2.2.7 [Kang]: Chapter 3 [Uyemura] Section 1.1, 1.2 (Excellent treatment on Vt) [Baker]: Section 6.1, 6.2, 6.3
  • [Suggested Problems]: [Hodges] Example 2.1,2.2,2.3,2.4,2.5,2.11, Prob. 2.1,2.4,2.5,2.7,2.8
  • [Additional Materials]: MOSFET Capacitance [Notes] || [Video]
• [Nov-12] Session-1 Modeling of MOS Device for Circuit Simulation. Session-2: Introduction to Lab on Cloud. Session-3: Parameter Extraction. MOS Problem discussion. [Video: Session-1 | Session-2 | Session-3]
  • [Suggested Reading]: [Hodges] Section 3.4, 3.5, 3.6, Appendix-A, NGSpice Manual
  • [Lab Assignment] MOS Parameter extraction and MOS Level-1 Modeling Link-to-PDK
• [Nov-13] Session-1: Intorduction to Linux. Session-2: Lab-1 -- Parameter extraction. [Video: Session-1 | Session-2]
  • [Assignment] Session-1: Solving problems related MOS Device. Session-2: Lab-2 Parameter extraction (contd.) [Video: Session-1 | Session-2]