Only available on weekends
ASIC verification Engineer with 5 years of Experience
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Mirafra Software Technologies
- Bangalore
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10:14
(UTC -12:00) - in/shriram-97
Popular repositories Loading
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Project_AXI4
Project_AXI4 PublicThis project is aimed to develop an complete VIP for AXI4.
SystemVerilog
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AXI_FIFO_BFM
AXI_FIFO_BFM PublicForked from apriya-ram/AXI_FIFO_BFM
AXI4 with a FIFO integrated with VIP
SystemVerilog
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pulpino__i2c_master__ip_verification
pulpino__i2c_master__ip_verification PublicForked from mbits-mirafra/pulpino__i2c_master__ip_verification
IP Veriification of I2C master using the I3C VIP
SystemVerilog
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