GitHub - sasquash21/Intro-to-VHDL-UDEMY: Learned to write VHDL in this Udemy course. I reinforced some of the things I learned in my undergrad like state machines. I was encouraged to take this course due to my embedded systems lab class in college in which they included Verilog but in a lackluster way. I intended to take this course to understand hardware description languages.

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Learned to write VHDL in this Udemy course. I reinforced some of the things I learned in my undergrad like state machines. I was encouraged to take this course due to my embedded systems lab class in college in which they included Verilog but in a lackluster way. I intended to take this course to understand hardware description languages.