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1 parent 16e4870 commit 8b26dc3Copy full SHA for 8b26dc3
src/register/mstatus.rs
@@ -142,6 +142,12 @@ impl Mstatus {
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}
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+ /// Modify Memory PRiVilege
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+ #[inline]
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+ pub fn mprv(&self) -> bool {
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+ self.bits.get_bit(17)
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+ }
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+
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/// Permit Supervisor User Memory access
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#[inline]
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pub fn sum(&self) -> bool {
@@ -226,6 +232,9 @@ set_csr!(
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set_csr!(
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/// Machine Previous Interrupt Enable
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, set_mpie, 1 << 7);
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+set_clear_csr!(
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+ , set_mprv, clear_mprv, 1 << 17);
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set_clear_csr!(
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, set_sum, clear_sum, 1 << 18);
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