El2: Adding TTBR0_EL2, ESR_EL2, SCTLR_EL2, MAIR_EL2, TCR_EL2, and VM field to HCR_EL2 (#28)

* Adding the VM field to HCR_EL2, which enables a second stage of translation. As documented here: https://developer.arm.com/documentation/ddi0500/d/system-control/aarch64-register-descriptions/hypervisor-configuration-register

* adding TTBR0_EL2

* Adding ESR_EL2

* Adding SCTLR_EL2

* Adding MAIR_EL2

* More descriptive explanation for the VM field in HCR_EL2

* Adding TCR_EL2

Co-authored-by: landhb <landhb@users.noreply.github.com>

Author: landhb

src/regs/esr_el2.rs

@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2021 by the author(s)
+//
+// Author(s):
+//   - Andre Richter <andre.o.richter@gmail.com>
+//   - Berkus Decker <berkus+github@metta.systems>
+//   - Bradley Landherr <landhb@users.noreply.github.com>
+
+//! Exception Syndrome Register - EL2
+//!
+//! Holds syndrome information for an exception taken to EL2.
+
+use register::{cpu::RegisterReadOnly, register_bitfields};
+
+register_bitfields! {u64,
+    pub ESR_EL2 [
+
+        /// Reserved
+        RES0 OFFSET(37) NUMBITS(27) [],
+
+        /// Instruction Specific Syndrome 2. If a memory access generated by an ST64BV or ST64BV0
+        /// instruction generates a Data Abort for a Translation fault, Access flag fault, or 
+        /// Permission fault, then this field holds register specifier, Xs.
+        ///
+        /// For any other Data Abort, this field is RES0.
+        ISS2 OFFSET(32) NUMBITS(5) [],
+
+        /// Exception Class. Indicates the reason for the exception that this register holds
+        /// information about.
+        ///
+        /// For each EC value, the table references a subsection that gives information about:
+        ///   - The cause of the exception, for example the configuration required to enable the
+        ///     trap.
+        ///   - The encoding of the associated ISS.
+        ///
+        /// Incomplete listing - to be done.
+        EC  OFFSET(26) NUMBITS(6) [
+            Unknown               = 0b00_0000,
+            TrappedWFIorWFE       = 0b00_0001,
+            TrappedMCRorMRC       = 0b00_0011, // A32
+            TrappedMCRRorMRRC     = 0b00_0100, // A32
+            TrappedMCRorMRC2      = 0b00_0101, // A32
+            TrappedLDCorSTC       = 0b00_0110, // A32
+            TrappedFP             = 0b00_0111,
+            TrappedMRRC           = 0b00_1100, // A32
+            BranchTarget          = 0b00_1101,
+            IllegalExecutionState = 0b00_1110,
+            SVC32                 = 0b01_0001, // A32
+            SVC64                 = 0b01_0101,
+            HVC64                 = 0b01_0110,
+            SMC64                 = 0b01_0111,
+            TrappedMsrMrs         = 0b01_1000,
+            TrappedSve            = 0b01_1001,
+            PointerAuth           = 0b01_1100,
+            InstrAbortLowerEL     = 0b10_0000,
+            InstrAbortCurrentEL   = 0b10_0001,
+            PCAlignmentFault      = 0b10_0010,
+            DataAbortLowerEL      = 0b10_0100,
+            DataAbortCurrentEL    = 0b10_0101,
+            SPAlignmentFault      = 0b10_0110,
+            TrappedFP32           = 0b10_1000, // A32
+            TrappedFP64           = 0b10_1100,
+            SError                = 0b10_1111,
+            BreakpointLowerEL     = 0b11_0000,
+            BreakpointCurrentEL   = 0b11_0001,
+            SoftwareStepLowerEL   = 0b11_0010,
+            SoftwareStepCurrentEL = 0b11_0011,
+            WatchpointLowerEL     = 0b11_0100,
+            WatchpointCurrentEL   = 0b11_0101,
+            Bkpt32                = 0b11_1000, // A32 BKTP instruction
+            Brk64                 = 0b11_1100  // A64 BRK instruction
+        ],
+
+        /// Instruction Length for synchronous exceptions.
+        IL  OFFSET(25) NUMBITS(1) [],
+
+        /// Instruction Specific Syndrome. Architecturally, this field can be defined independently
+        /// for each defined Exception class. However, in practice, some ISS encodings are used for
+        /// more than one Exception class.
+        ISS OFFSET(0)  NUMBITS(25) []
+    ]
+}
+
+pub struct Reg;
+
+impl RegisterReadOnly<u64, ESR_EL2::Register> for Reg {
+    sys_coproc_read_raw!(u64, "ESR_EL2", "x");
+}
+
+pub static ESR_EL2: Reg = Reg {};

src/regs/hcr_el2.rs

@@ -4,6 +4,7 @@
 //
 // Author(s):
 //   - Andre Richter <andre.o.richter@gmail.com>
+//   - Bradley Landherr <landhb@users.noreply.github.com>
 
 //! Hypervisor Configuration Register - EL2
 //!
@@ -89,7 +90,26 @@ register_bitfields! {u64,
         ///
         /// When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other
         /// than a direct read of this field.
-        SWIO OFFSET(1) NUMBITS(1) []
+        SWIO OFFSET(1) NUMBITS(1) [],
+
+        /// Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime,
+        /// when EL2 is enabled in the current Security state. The possible values are:
+        ///
+        /// 0    EL1&0 stage 2 address translation disabled. 
+        /// 1    EL1&0 stage 2 address translation enabled.
+        /// 
+        /// When the value of this bit is 1, data cache invalidate instructions executed at EL1 perform
+        /// a data cache clean and invalidate. For the invalidate by set/way instruction this behavior 
+        /// applies regardless of the value of the HCR_EL2.SWIO bit.
+        ///
+        /// This bit is permitted to be cached in a TLB.
+        ///
+        /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this
+        /// field behaves as 0 for all purposes other than a direct read of the value of this field.
+        VM OFFSET(0) NUMBITS(1) [
+            Disable = 0,
+            Enable = 1
+        ]
     ]
 }