Add TCR_EL1 A1 Constants

Author: andre-richter

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "cortex-a"
-version = "5.1.4"
+version = "5.1.5"
 authors = ["Andre Richter <andre.o.richter@gmail.com>"]
 description = "Low level access to Cortex-A processors"
 homepage = "https://github.com/rust-embedded/cortex-a"

src/regs/tcr_el1.rs

@@ -33,22 +33,23 @@ register_bitfields! {u64,
         ///     Reserved, RES0.
         TBID0  OFFSET(51) NUMBITS(1) [],
 
-        /// Top Byte ignored - indicates whether the top byte of an address is
-        /// used for address match for the TTBR1_EL1 region, or ignored and used
-        /// for tagged addresses. Defined values are:
+        /// Top Byte ignored - indicates whether the top byte of an address is used for address
+        /// match for the TTBR1_EL1 region, or ignored and used for tagged addresses. Defined values
+        /// are:
         ///
         /// 0 Top Byte used in the address calculation.
+        ///
         /// 1 Top Byte ignored in the address calculation.
         ///
-        /// This affects addresses generated in EL0 and EL1 using AArch64 where
-        /// the address would be translated by tables pointed to by TTBR1_EL1.
-        /// It has an effect whether the EL1&0 translation regime is enabled or not.
+        /// This affects addresses generated in EL0 and EL1 using AArch64 where the address would be
+        /// translated by tables pointed to by TTBR1_EL1. It has an effect whether the EL1&0
+        /// translation regime is enabled or not.
         ///
-        /// If ARMv8.3-PAuth is implemented and TCR_EL1.TBID1 is 1, then this field
-        /// only applies to Data accesses.
-        /// Otherwise, if the value of TBI1 is 1 and bit [55] of the target address
-        /// to be stored to the PC is 0, then bits[63:56] of that target address are
-        /// also set to 0 before the address is stored in the PC, in the following cases:
+        /// If ARMv8.3-PAuth is implemented and TCR_EL1.TBID1 is 1, then this field only applies to
+        /// Data accesses.
+        /// Otherwise, if the value of TBI1 is 1 and bit [55] of the target address to be stored to
+        /// the PC is 0, then bits[63:56] of that target address are also set to 0 before the
+        /// address is stored in the PC, in the following cases:
         ///
         /// • A branch or procedure return within EL0 or EL1.
         /// • An exception taken to EL1.
@@ -58,22 +59,23 @@ register_bitfields! {u64,
             Ignored = 1
         ],
 
-        /// Top Byte ignored - indicates whether the top byte of an address is
-        /// used for address match for the TTBR0_EL1 region, or ignored and used
-        /// for tagged addresses. Defined values are:
+        /// Top Byte ignored - indicates whether the top byte of an address is used for address
+        /// match for the TTBR0_EL1 region, or ignored and used for tagged addresses. Defined values
+        /// are:
         ///
         /// 0 Top Byte used in the address calculation.
+        ///
         /// 1 Top Byte ignored in the address calculation.
         ///
-        /// This affects addresses generated in EL0 and EL1 using AArch64 where
-        /// the address would be translated by tables pointed to by TTBR0_EL1.
-        /// It has an effect whether the EL1&0 translation regime is enabled or not.
+        /// This affects addresses generated in EL0 and EL1 using AArch64 where the address would be
+        /// translated by tables pointed to by TTBR0_EL1. It has an effect whether the EL1&0
+        /// translation regime is enabled or not.
         ///
-        /// If ARMv8.3-PAuth is implemented and TCR_EL1.TBID0 is 1, then this field
-        /// only applies to Data accesses.
-        /// Otherwise, if the value of TBI0 is 1 and bit [55] of the target address
-        /// to be stored to the PC is 0, then bits[63:56] of that target address are
-        /// also set to 0 before the address is stored in the PC, in the following cases:
+        /// If ARMv8.3-PAuth is implemented and TCR_EL1.TBID0 is 1, then this field only applies to
+        /// Data accesses.
+        /// Otherwise, if the value of TBI0 is 1 and bit [55] of the target address to be stored to
+        /// the PC is 0, then bits[63:56] of that target address are also set to 0 before the
+        /// address is stored in the PC, in the following cases:
         ///
         /// • A branch or procedure return within EL0 or EL1.
         /// • An exception taken to EL1.
@@ -85,12 +87,12 @@ register_bitfields! {u64,
 
         /// ASID Size. Defined values are:
         ///
-        /// 0 8 bit - the upper 8 bits of TTBR0_EL1 and TTBR1_EL1 are ignored by hardware
-        ///           for every purpose except reading back the register, and are treated
-        ///           as if they are all zeros for when used for allocation and matching
-        ///           entries in the TLB.
-        /// 1 16 bit - the upper 16 bits of TTBR0_EL1 and TTBR1_EL1 are used for allocation
-        ///            and matching in the TLB.
+        /// 0 8 bit - the upper 8 bits of TTBR0_EL1 and TTBR1_EL1 are ignored by hardware for every
+        ///           purpose except reading back the register, and are treated as if they are all
+        ///           zeros for when used for allocation and matching entries in the TLB.
+        ///
+        /// 1 16 bit - the upper 16 bits of TTBR0_EL1 and TTBR1_EL1 are used for allocation and
+        ///            matching in the TLB.
         ///
         /// If the implementation has only 8 bits of ASID, this field is RES0.
         AS  OFFSET(36) NUMBITS(1) [
@@ -212,19 +214,23 @@ register_bitfields! {u64,
             DisableTTBR1Walks = 1
         ],
 
-        /// Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID.
-        /// The encoding of this bit is:
+        /// Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding of this bit is:
         ///
         /// 0 TTBR0_EL1.ASID defines the ASID.
         /// 1 TTBR1_EL1.ASID defines the ASID.
-        A1  OFFSET(22) NUMBITS(1) [],
+        A1  OFFSET(22) NUMBITS(1) [
+            TTBR0 = 0,
+            TTBR1 = 1
+        ],
 
-        /// The size offset of the memory region addressed by TTBR0_EL1. The region size is
-        /// 2^(64-T0SZ) bytes.
+        /// The size offset of the memory region addressed by TTBR1_EL1. The region size is
+        /// 2^(64-T1SZ) bytes.
         ///
-        /// The maximum and minimum possible values for T0SZ depend on the level of translation
+        /// The maximum and minimum possible values for T1SZ depend on the level of translation
         /// table and the memory translation granule size, as described in the AArch64 Virtual
         /// Memory System Architecture chapter.
+        ///
+        /// This field resets to an architecturally UNKNOWN value.
         T1SZ  OFFSET(16) NUMBITS(6) [],
 
         /// Granule size for the TTBR0_EL1.