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Add unratified Smclic, Ssclic, Smclicshv extensions #420

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Add unratified Smclic, Ssclic, Smclicshv extensions #420

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5819f81
Add unratified Smclic, Ssclic, Smclicshv extensions
dansmathers Mar 1, 2024
0288a3d
Add unratified Smclic, Ssclic, Smclicshv extensions
dansmathers Mar 1, 2024
0224391
Add unratified Smclic, Ssclic, Smclicshv extensions
dansmathers Mar 1, 2024
0edd11e
Add unratified Smclic, Ssclic, Smclicshv extensions
dansmathers Mar 1, 2024
0a65ab1
Add unratified Smclic, Ssclic, Smclicshv extensions
dansmathers Mar 1, 2024
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5 changes: 5 additions & 0 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -64,9 +64,11 @@ SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.s
SAIL_SYS_SRCS = riscv_csr_map.sail
SAIL_SYS_SRCS += riscv_vext_control.sail # helpers for the 'V' extension
SAIL_SYS_SRCS += riscv_next_regs.sail
SAIL_SYS_SRCS += riscv_clic_regs.sail # Smclic/Ssclic extensions
SAIL_SYS_SRCS += riscv_sys_exceptions.sail # default basic helpers for exception handling
SAIL_SYS_SRCS += riscv_sync_exception.sail # define the exception structure used in the model
SAIL_SYS_SRCS += riscv_next_control.sail # helpers for the 'N' extension
SAIL_SYS_SRCS += riscv_clic_control.sail # helpers for the Smclic/Ssclic extensions
SAIL_SYS_SRCS += riscv_softfloat_interface.sail riscv_fdext_regs.sail riscv_fdext_control.sail
SAIL_SYS_SRCS += riscv_csr_ext.sail # access to CSR extensions
SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling
Expand All @@ -88,11 +90,14 @@ SAIL_REGS_SRCS = riscv_reg_type.sail riscv_freg_type.sail riscv_regs.sail riscv_
SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail
SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
SAIL_REGS_SRCS += riscv_vreg_type.sail riscv_vext_regs.sail
SAIL_REGS_SRCS += riscv_clic_type.sail # Smclic/Ssclic extensions

SAIL_ARCH_SRCS = $(PRELUDE)
SAIL_ARCH_SRCS += riscv_types_common.sail riscv_types_ext.sail riscv_types.sail
SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS)
SAIL_ARCH_SRCS += riscv_clic_mem.sail # clic vector table fetch uses mem_read in riscv_mem.sail

SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail
SAIL_ARCH_SRCS += riscv_types_kext.sail # Shared/common code for the cryptography extension.

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10 changes: 10 additions & 0 deletions c_emulator/riscv_platform.c
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Expand Up @@ -113,6 +113,16 @@ mach_bits plat_clint_size(unit u)
return rv_clint_size;
}

mach_bits plat_clic_base(unit u)
{
return rv_clic_base;
}

mach_bits plat_clic_size(unit u)
{
return rv_clic_size;
}

unit load_reservation(mach_bits addr)
{
reservation = addr;
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3 changes: 3 additions & 0 deletions c_emulator/riscv_platform.h
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Expand Up @@ -29,6 +29,9 @@ mach_bits plat_get_16_random_bits();
mach_bits plat_clint_base(unit);
mach_bits plat_clint_size(unit);

mach_bits plat_clic_base(unit);
mach_bits plat_clic_size(unit);

bool speculate_conditional(unit);
unit load_reservation(mach_bits);
bool match_reservation(mach_bits);
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3 changes: 3 additions & 0 deletions c_emulator/riscv_platform_impl.c
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Expand Up @@ -42,6 +42,9 @@ uint64_t rv_16_random_bits(void)
uint64_t rv_clint_base = UINT64_C(0x2000000);
uint64_t rv_clint_size = UINT64_C(0xc0000);

uint64_t rv_clic_base = UINT64_C(0x4000000);
uint64_t rv_clic_size = UINT64_C(0xc0000);

uint64_t rv_htif_tohost = UINT64_C(0x80001000);
uint64_t rv_insns_per_tick = UINT64_C(100);

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3 changes: 3 additions & 0 deletions c_emulator/riscv_platform_impl.h
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Expand Up @@ -34,6 +34,9 @@ extern uint64_t rv_16_random_bits(void);
extern uint64_t rv_clint_base;
extern uint64_t rv_clint_size;

extern uint64_t rv_clic_base;
extern uint64_t rv_clic_size;

extern uint64_t rv_htif_tohost;
extern uint64_t rv_insns_per_tick;

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2 changes: 2 additions & 0 deletions c_emulator/riscv_sim.c
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Expand Up @@ -616,6 +616,8 @@ void init_sail(uint64_t elf_entry)
rv_rom_size = UINT64_C(0);
rv_clint_base = UINT64_C(0);
rv_clint_size = UINT64_C(0);
rv_clic_base = UINT64_C(0);
rv_clic_size = UINT64_C(0);
rv_htif_tohost = UINT64_C(0);
zPC = elf_entry;
} else
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8 changes: 8 additions & 0 deletions handwritten_support/riscv_extras.lem
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Expand Up @@ -193,6 +193,14 @@ val plat_clint_size : unit -> bitvector
let plat_clint_size () = []
declare ocaml target_rep function plat_clint_size = `Platform.clint_size`

val plat_clic_base : unit -> bitvector
let plat_clic_base () = []
declare ocaml target_rep function plat_clic_base = `Platform.clic_base`

val plat_clic_size : unit -> bitvector
let plat_clic_size () = []
declare ocaml target_rep function plat_clic_size = `Platform.clic_size`

val plat_enable_dirty_update : unit -> bool
let plat_enable_dirty_update () = false
declare ocaml target_rep function plat_enable_dirty_update = `Platform.enable_dirty_update`
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8 changes: 8 additions & 0 deletions handwritten_support/riscv_extras_sequential.lem
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Expand Up @@ -181,6 +181,14 @@ val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a
let plat_clint_size () = wordFromInteger 0
declare ocaml target_rep function plat_clint_size = `Platform.clint_size`

val plat_clic_base : forall 'a. Size 'a => unit -> bitvector 'a
let plat_clic_base () = wordFromInteger 0
declare ocaml target_rep function plat_clic_base = `Platform.clic_base`

val plat_clic_size : forall 'a. Size 'a => unit -> bitvector 'a
let plat_clic_size () = wordFromInteger 0
declare ocaml target_rep function plat_clic_size = `Platform.clic_size`

val plat_enable_dirty_update : unit -> bool
let plat_enable_dirty_update () = false
declare ocaml target_rep function plat_enable_dirty_update = `Platform.enable_dirty_update`
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