chore(deps): bump ext/riscv-isa-manual from 5202d9c to a0e6b7a
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Bumps [ext/riscv-isa-manual](https://github.com/riscv/riscv-isa-manual) from `5202d9c` to `a0e6b7a`. - [Release notes](https://github.com/riscv/riscv-isa-manual/releases) - [Commits](riscv/riscv-isa-manual@5202d9c...a0e6b7a) --- updated-dependencies: - dependency-name: ext/riscv-isa-manual dependency-version: a0e6b7af968762f235f714b52af34e21e22144de dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Bumps ext/riscv-isa-manual from
5202d9ctoa0e6b7a.Commits
a0e6b7aDescribe mask tail handling consistently (#2118)0b4a55aFix some references to illegal-instruction exceptions that should be reserved...3e36c55Remove unary pluses from vector operations (#2115)a375b61Fix a double space (#2116)300f97bImprove description of vector register group overlap constraints (#2113)b5a4f6dFix copy/paste error, correcting hideleg to 'interrupt' rather than 'exceptio...a35c6f4Mark GitHub-generated releases as "Intermediate Releases" (#2111)208590eFix vector example appendix as separate from previous. (#2106)2430b2aMerge pull request #2104 from riscv/2089-how-should-the-sireg2vsireg2-registe...6221268Update smcdeleg.adocDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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