docs(Q): add instruction metadata for Q extension (quad-precision)

spec/std/isa/inst/Q/fclass.q.yaml

@@ -6,9 +6,35 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fclass.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Classify
+description:
+  - id: inst-fclass.q-behaviour
+    normative: false
+    text: |
+      The `fclass.q` instruction examines the value in floating-point register `rs1` and writes to integer
+      register `rd` a 10-bit mask that indicates the class of the floating-point number.
+
+      The format of the mask is described in table given below. The corresponding bit in `rd`
+      will be set if the property is true and clear otherwise. All other bits in `rd` are cleared.
+
+      Note that exactly one bit in `rd` will be set. `fclass.q` does not set the floating-point
+      exception flags.
+
+      .Format of result of `fclass` instruction.
+      [%autowidth,float="center",align="center",cols="^,<",options="header",]
+      |===
+      |_xd_ bit |Meaning
+      |0 |_fs1_ is latexmath:[$-\infty$].
+      |1 |_fs1_ is a negative normal number.
+      |2 |_fs1_ is a negative subnormal number.
+      |3 |_fs1_ is latexmath:[$-0$].
+      |4 |_fs1_ is latexmath:[$+0$].
+      |5 |_fs1_ is a positive subnormal number.
+      |6 |_fs1_ is a positive normal number.
+      |7 |_fs1_ is latexmath:[$+\infty$].
+      |8 |_fs1_ is a signaling NaN.
+      |9 |_fs1_ is a quiet NaN.
+      |===
 definedBy: Q
 assembly: xd, fs1
 encoding:

spec/std/isa/inst/Q/fdiv.q.yaml

@@ -6,9 +6,19 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fdiv.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Divide
+description:
+  - id: inst-fdiv.q-behaviour
+    normative: false
+    text: |
+      The `fdiv.q` performs the quad-precision floating-point division of `fs1` by `fs2` and writes
+      the result to floating-point register `fd`.`
+      The rounding mode is specified by the value in the floating-point Control and Status register (FCSR)
+      or by the value in the `rm` field of the instruction.
+
+      The operation is performed according to the IEEE 754-2008 standard for quad-precision floating-point arithmetic.
+
+      The instruction sets the floating-point exception flags according to the result of the operation.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:

spec/std/isa/inst/Q/feq.q.yaml

@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: feq.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Equal
+description:
+  - id: inst-feq.q-behaviour
+    normative: false
+    text: |
+      The `feq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
+
+      `feq.q` performs a quiet comparison:
+      it only sets the invalid operation exception flag if either input is a signaling _NaN_.
+      The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:

spec/std/isa/inst/Q/fle.q.yaml

@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fle.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Less Than or Equal
+description:
+  - id: inst-fle.q-behaviour
+    normative: false
+    text: |
+      The `fle.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+      `fle.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
+      they set the invalid operation exception flag if either input is _NaN_.
+      The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:

spec/std/isa/inst/Q/fleq.q.yaml

@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fleq.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Less Than or Equal
+description:
+  - id: inst-fleq.q-behaviour
+    normative: false
+    text: |
+      The `fleq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+      `fleq.q` is defined like `fle.q`, except that quiet _NaN_ inputs do not cause the invalid
+      operation exception flag to be set.
+      This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: xd, fs1, fs2

spec/std/isa/inst/Q/fli.q.yaml

@@ -6,9 +6,15 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fli.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Load Immediate
+description:
+  - id: inst-fli.q-behaviour
+    normative: false
+    text: |
+      The
+      The `fli.q` instruction loads one of 32 quad-precision floating-point constants, encoded in the `rs1`
+      field, into floating-point register `rd`.
+      `fli.q` is encoded like `fmv.w.x`, but with _fmt_ = Q.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, xs1

spec/std/isa/inst/Q/flq.yaml

@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: flq
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Load
+description:
+  - id: inst-flq-behaviour
+    normative: false
+    text: |
+      The `flq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
+
+      `flq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
+
+      `flq` does not modify the bits being transferred; in particular, the payloads of non-canonical
+      _NaNs_ are preserved.
 definedBy: Q
 assembly: fd, xs1, imm
 encoding:

spec/std/isa/inst/Q/flt.q.yaml

@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: flt.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Less Than
+description:
+  - id: inst-flt.q-behaviour
+    normative: false
+    text: |
+      The `flt.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
+
+      `flt.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
+      they set the invalid operation exception flag if either input is _NaN_.
+      The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:

spec/std/isa/inst/Q/fltq.q.yaml

@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fltq.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Quiet Less Than
+description:
+  - id: inst-fltq.q-behaviour
+    normative: false
+    text: |
+      The `fltq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+      `fltq.q` is defined like `flt.q`, except that quiet _NaN_ inputs do not cause the invalid
+      operation exception flag to be set.
+      This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2

spec/std/isa/inst/Q/fmadd.q.yaml

@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmadd.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Fused Multiply-Add
+description:
+  - id: inst-fmadd.q-behaviour
+    normative: true
+    text: |
+      The `fmadd.q` instruction performs a floating-point multiply-add operation on the values in registers `fs1`, `fs2`, and `fs3`.
+      It computes the result as `(fs1 * fs2) + fs3` and writes the result to the destination register `fd`.
+
+      The fused multiply-add instructions must set the invalid operation exception flag when the
+      multiplicands are latexmath:[$\infty$] and zero, even when the addend is a quiet _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:

spec/std/isa/inst/Q/fmax.q.yaml

@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmax.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Maximum-Number
+description:
+  - id: inst-fmax.q-behaviour
+    normative: false
+    text: |
+      The `fmax.q` instruction writes the larger/maximum of `fs1` and `fs2` to `fd`.
+      The value `-0.0` is considered to be less than the value `+0.0`.
+      If both inputs are _NaN_s, the result is the canonical _NaN_.
+      If only one operand is a _NaN_, the result is the non-_NaN_ operand.
+      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:

spec/std/isa/inst/Q/fmaxm.q.yaml

@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmaxm.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Maximum-Number with _NaN_ Handling
+description:
+  - id: inst-fmaxm.q-behaviour
+    normative: false
+    text: |
+      The `fmaxm.q` instruction, defined like `fmax.q`, writes the larger/maximum of `fs1` and `fs2` to `fd`.
+      The value `-0.0` is considered to be less than the value `+0.0`.
+      If both inputs are _NaN_s, the result is the canonical _NaN_.
+      If either input is _NaN_, the result is the canonical _NaN_.
+      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+      This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2

spec/std/isa/inst/Q/fmin.q.yaml

@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmin.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Minimum-Number
+description:
+  - id: inst-fmin.q-behaviour
+    normative: false
+    text: |
+      The `fmin.q` instruction writes the smaller/minimum of `fs1` and `fs2` to `fd`.
+      The value `-0.0` is considered to be less than the value `+0.0`.
+      If both inputs are _NaN_s, the result is the canonical _NaN_.
+      If only one operand is a _NaN_, the result is the non-_NaN_ operand.
+      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:

spec/std/isa/inst/Q/fminm.q.yaml

@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fminm.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Minimum-Number with _NaN_ Handling
+description:
+  - id: inst-fminm.q-behaviour
+    normative: false
+    text: |
+      The `fminm.q` instruction, defined like `fmin.q`, writes the smaller/minimum of `fs1` and `fs2` to `fd`.
+      The value `-0.0` is considered to be less than the value `+0.0`.
+      If both inputs are _NaN_s, the result is the canonical _NaN_.
+      If either input is _NaN_, the result is the canonical _NaN_.
+      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+      This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2

spec/std/isa/inst/Q/fmsub.q.yaml

@@ -6,9 +6,13 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmsub.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Fused Multiply-Subtract
+description:
+  - id: inst-fmsub.q-behaviour
+    normative: false
+    text: |
+      The `fmsub.q` instruction performs a floating-point multiply-subtract operation on the values in registers `fs1`, `fs2`, and `fs3`.
+      It computes the result as `(fs1 * fs2) - fs3` and writes the result to the destination register `fd`.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:

spec/std/isa/inst/Q/fmul.q.yaml

@@ -6,9 +6,12 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmul.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Multiply
+description:
+  - id: inst-fmul.q-behaviour
+    normative: false
+    text: |
+      `fmul.q` performs quad-precision floating-point multiplication, between `fs1` and `fs2`.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:

spec/std/isa/inst/Q/fmvh.x.q.yaml

@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmvh.x.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Move Upper 64 Bits of Quad-Precision Floating-Point to Integer Register
+description:
+  - id: inst-fmvh.x.q-behaviour
+    normative: false
+    text: |
+      The `fmvh.x.q` instruction moves bits `127:64` of floating-point register `fs1` into integer register `xd`.
+      It is encoded in the OP-FP major opcode with _funct3_=0, _rs2_=1, and _funct7_=1110011.
+
+      `fmvh.x.q` is used in conjunction with the existing `fmv.x.d` instruction to move a quad-precision floating-point
+      number to a pair of x-registers.
 definedBy:
   allOf: [Q, Zfa]
 base: 64

spec/std/isa/inst/Q/fmvp.q.x.yaml

@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmvp.q.x
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Move Integer Pair to Quad-Precision
+description:
+  - id: inst-fmvp.q.x-behaviour
+    normative: false
+    text: |
+      The `fmvp.q.x` instruction moves a double-precision number from a pair of integer registers into
+      a floating-point register.
+      Integer registers xs1 and xs2 supply bits 63:0 and 127:64, respectively; the result is written to
+      floating-point register `fd`.
+      `fmvp.q.x` is encoded in the OP-FP major opcode with _funct3_=0 and _funct7_=1011011.
 definedBy:
   allOf: [Q, Zfa]
 base: 64

spec/std/isa/inst/Q/fnmadd.q.yaml

@@ -6,9 +6,14 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fnmadd.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Fused Negate-Multiply-Add
+description:
+  - id: inst-fnmadd.q-behaviour
+    normative: true
+    text: |
+      The `fnmadd.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the
+      value in `fs3`, and writes the final result to `fd`.
+      `fnmadd.q` computes `-(fs1 * fs2) + fs3`.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding: