Modify Smaia extension and add Machine-Level AIA CSRs (Phase 1 of Issue #566) #851
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| RESERVED: | ||
| location: 31-28 | ||
| base: 32 | ||
| type: RO | ||
| reset_value: 0 | ||
| description: Reserved. Always reads as 0. |
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Just remove this; unspecified bits are reserved
| Bits corresponding to unsupported or unimplemented interrupts must be read-only zero. | ||
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| fields: | ||
| midelegh: |
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field names need to be UPPERCASE
| location: 31-0 | ||
| type: RW-R | ||
| sw_write(csr_value): | | ||
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| description: | | ||
| Interrupt delegation bits 32-63. Each bit, when set, delegates the corresponding | ||
| interrupt to HS/S-mode. Bits corresponding to unimplemented or non-delegatable interrupts | ||
| are read-only zero. | ||
| reset_value: 0 |
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Unlike the spec, UDB treats the individual bits of m[i|e]deleg as separate fields. In this case, I think there aren't any standard interrupts > 31, so this CSR has an empty fields right now:
fields: []
| mieh: | ||
| location: 31-0 | ||
| type: RW-R | ||
| sw_write(csr_value): | | ||
| description: | | ||
| Interrupt enable bits 32-63. Each bit enables the corresponding interrupt | ||
| if supported. Unsupported bits are read-only zero. | ||
| reset_value: 0 |
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same here, empty fields
| location: 31-0 | ||
| type: RW | ||
| description: | | ||
| Interrupt-pending bits 32 through 63. Each bit corresponds to an interrupt | ||
| source above bit 31 in the full `mip` register. These bits reflect interrupt | ||
| pending status and are writable in M-mode. | ||
| reset_value: 0 |
| IPRIO: | ||
| location: 7-0 | ||
| base: 32 | ||
| type: RO |
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should be RO-H (read only with hardware update)
| IID: | ||
| location: 27-16 | ||
| base: 32 | ||
| type: RO |
| description: | | ||
| Supervisor software interrupt enable. May be writable or read-only zero depending on platform. | ||
| When 1, allows delegation of SSIP via `mvip` even if not delegated via `mideleg`. |
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we need a parameter for this. it will affect type(), and probably reset_value()
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This one is complicated. We have to represent this:
Which means that we have to change sip and sie defintions.
This PR introduces initial support for the Smaia (Machine-Level Advanced Interrupt Architecture) extension, addressing Issue #566.
New Machine-Level CSRs Added:
These CSRs represent Phase 1 of the implementation, covering machine-level functionality. Supervisor- and VS-level CSRs will be added in a follow-up phase.