Add Smstateen/Ssstateen Extension and CSRs

arch/csr/hstateen0.yaml

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+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hstateen0
+long_name: Hypervisor State Enable 0 Register
+address: 0x60C
+priv_mode: S
+length: 64
+description: |
+  For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR.
+  Bit 63 of hstateen0 controls access to sstateen0.
+
+  With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen
+  CSRs, except controlling accesses for a virtual machine (from VS and VU modes).
+
+  For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in sstateen when accessed in VS-mode.
+
+  A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one
+  in the matching mstateen CSR.
+
+definedBy:
+  allOf:
+    - H
+    - Smstateen
+    - Ssstateen
+fields:
+  SEO:
+    location: 63
+    description: |
+      The SE0 bit in hstateen0 controls access to the sstateen0 CSR.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  ENVCFG:
+    location: 62
+    description: |
+      The ENVCFG bit in hstateen0 controls access to the senvcfg CSRs.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  CSRIND:
+    location: 60
+    description: |
+      The CSRIND bit in hstateen0 controls access to the siselect and the
+      sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind
+      extensions.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  AIA:
+    location: 59
+    description: |
+      The AIA bit in hstateen0 controls access to all state introduced by
+      the Ssaia extension and is not controlled by either the CSRIND or the
+      IMSIC bits of hstateen0.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  IMSIC:
+    location: 58
+    description: |
+      The IMSIC bit in hstateen0 controls access to the guest IMSIC state,
+      including CSRs stopei (really vstopei), provided by the Ssaia extension.
+
+      Setting the IMSIC bit in hstateen0 to zero prevents a virtual machine
+      from accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  CONTEXT:
+    location: 57
+    description: |
+      The CONTEXT bit in hstateen0 controls access to the scontext CSR provided
+      by the Sdtrig extension.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  JVT:
+    location: 2
+    description: |
+      The JVT bit controls access to the jvt CSR provided by the Zcmt extension.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  FCSR:
+    location: 1
+    description: |
+      The FCSR bit controls access to fcsr for the case when floating-point instructions
+      operate on x registers instead of f registers as specified by the Zfinx and related
+      extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only
+      zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience,
+      when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a
+      controlling stateen0 CSR is zero, all floating-point instructions cause an illegal
+      instruction trap (or virtual instruction trap, if relevant), as though they all access
+      fcsr, regardless of whether they really do.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  C:
+    location: 0
+    description: |
+      The C bit controls access to any and all custom state. This bit is not custom state itself.
+      The C bit of these registers is not custom state itself; it is a standard field of a
+      standard CSR, either mstateen0, hstateen0, or sstateen0.
+    type: RW
+    reset_value: UNDEFINED_LEGAL

arch/csr/hstateen0h.yaml

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+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hstateen0h
+long_name: Upper 32 bits of Hypervisor State Enable 0 Register
+address: 0x61C
+priv_mode: S
+length: 32
+description: |
+  For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0),
+  mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at
+  supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented,
+  another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3.
+
+  For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
+  set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h,
+  hstateen1h, hstateen2h, and hstateen3h.
+
+definedBy:
+  allOf:
+    - H
+    - Smstateen
+    - Ssstateen
+fields:
+  SEO:
+    location: 31
+    description: |
+      The SE0 bit in hstateen0h controls access to the sstateen0 CSR.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  ENVCFG:
+    location: 30
+    description: |
+      The ENVCFG bit in hstateen0h controls access to the senvcfg CSRs.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  CSRIND:
+    location: 28
+    description: |
+      The CSRIND bit in hstateen0h controls access to the siselect and the
+      sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind
+      extensions.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  AIA:
+    location: 27
+    description: |
+      The AIA bit in hstateen0h controls access to all state introduced by
+      the Ssaia extension and is not controlled by either the CSRIND or the
+      IMSIC bits of hstateen0.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  IMSIC:
+    location: 26
+    description: |
+      The IMSIC bit in hstateen0h controls access to the guest IMSIC state,
+      including CSRs stopei (really vstopei), provided by the Ssaia extension.
+
+      Setting the IMSIC bit in hstateen0h to zero prevents a virtual machine
+      from accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+  CONTEXT:
+    location: 25
+    description: |
+      The CONTEXT bit in hstateen0h controls access to the scontext CSR provided
+      by the Sdtrig extension.
+    type: RW
+    reset_value: UNDEFINED_LEGAL

arch/csr/hstateen1.yaml

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+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hstateen1
+long_name: Hypervisor State Enable 1 Register
+address: 0x60D
+priv_mode: S
+length: 64
+description: |
+  For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR.
+  Bit 63 of hstateen1 controls access to sstateen1.
+
+  With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen
+  CSRs, except controlling accesses for a virtual machine (from VS and VU modes).
+
+  For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in sstateen when accessed in VS-mode.
+
+  A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one
+  in the matching mstateen CSR.
+
+definedBy:
+  allOf:
+    - H
+    - Smstateen
+    - Ssstateen
+fields:
+  SEO:
+    location: 63
+    description: |
+      The SE0 bit in hstateen1 controls access to the sstateen1 CSR.
+    type: RW
+    reset_value: UNDEFINED_LEGAL

arch/csr/hstateen1h.yaml

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+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hstateen1h
+long_name: Upper 32 bits of Hypervisor State Enable 1 Register
+address: 0x61D
+priv_mode: S
+length: 32
+description: |
+  For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0),
+  mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at
+  supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented,
+  another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3.
+
+  For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
+  set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h,
+  hstateen1h, hstateen2h, and hstateen3h.
+
+definedBy:
+  allOf:
+    - H
+    - Smstateen
+    - Ssstateen
+fields:
+  SEO:
+    location: 31
+    description: |
+      The SE0 bit in hstateen1h controls access to the sstateen1 CSR.
+    type: RW
+    reset_value: UNDEFINED_LEGAL

arch/csr/hstateen2.yaml

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+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hstateen2
+long_name: Hypervisor State Enable 2 Register
+address: 0x60E
+priv_mode: S
+length: 64
+description: |
+  For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR.
+  Bit 63 of hstateen2 controls access to sstateen2.
+
+  With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen
+  CSRs, except controlling accesses for a virtual machine (from VS and VU modes).
+
+  For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in sstateen when accessed in VS-mode.
+
+  A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one
+  in the matching mstateen CSR.
+
+definedBy:
+  allOf:
+    - H
+    - Smstateen
+    - Ssstateen
+fields:
+  SEO:
+    location: 63
+    description: |
+      The SE0 bit in hstateen2 controls access to the sstateen2 CSR.
+    type: RW
+    reset_value: UNDEFINED_LEGAL

arch/csr/hstateen2h.yaml

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+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hstateen2h
+long_name: Upper 32 bits of Hypervisor State Enable 2 Register
+address: 0x61E
+priv_mode: S
+length: 32
+description: |
+  For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0),
+  mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at
+  supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented,
+  another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3.
+
+  For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
+  set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h,
+  hstateen1h, hstateen2h, and hstateen3h.
+
+definedBy:
+  allOf:
+    - H
+    - Smstateen
+    - Ssstateen
+fields:
+  SEO:
+    location: 31
+    description: |
+      The SE0 bit in hstateen2h controls access to the sstateen2 CSR.
+    type: RW
+    reset_value: UNDEFINED_LEGAL

arch/csr/hstateen3.yaml

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+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hstateen3
+long_name: Hypervisor State Enable 3 Register
+address: 0x60F
+priv_mode: S
+length: 64
+description: |
+  For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR.
+  Bit 63 of hstateen3 controls access to sstateen3.
+
+  With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen
+  CSRs, except controlling accesses for a virtual machine (from VS and VU modes).
+
+  For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in sstateen when accessed in VS-mode.
+
+  A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one
+  in the matching mstateen CSR.
+
+definedBy:
+  allOf:
+    - H
+    - Smstateen
+    - Ssstateen
+fields:
+  SEO:
+    location: 63
+    description: |
+      The SE0 bit in hstateen3 controls access to the sstateen3 CSR.
+    type: RW
+    reset_value: UNDEFINED_LEGAL

arch/csr/hstateen3h.yaml

@@ -0,0 +1,31 @@
+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hstateen3h
+long_name: Upper 32 bits of Hypervisor State Enable 3 Register
+address: 0x61F
+priv_mode: S
+length: 32
+description: |
+  For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0),
+  mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at
+  supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented,
+  another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3.
+
+  For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
+  set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h,
+  hstateen1h, hstateen2h, and hstateen3h.
+
+definedBy:
+  allOf:
+    - H
+    - Smstateen
+    - Ssstateen
+fields:
+  SEO:
+    location: 31
+    description: |
+      The SE0 bit in hstateen3h controls access to the sstateen3 CSR.
+    type: RW
+    reset_value: UNDEFINED_LEGAL