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| 1 | +# yaml-language-server: $schema=../../schemas/csr_schema.json |
| 2 | + |
| 3 | +$schema: "csr_schema.json#" |
| 4 | +kind: csr |
| 5 | +name: hstateen0 |
| 6 | +long_name: Hypervisor State Enable 0 Register |
| 7 | +address: 0x60C |
| 8 | +priv_mode: S |
| 9 | +length: 64 |
| 10 | +description: |
| 11 | + - id: csr-hstateen0-purpose |
| 12 | + normative: true |
| 13 | + text: | |
| 14 | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, |
| 15 | + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the |
| 16 | + FS and VS fields for the F and V extensions. |
| 17 | + - id: csr-hstateen0-num-justification |
| 18 | + normative: false |
| 19 | + text: | |
| 20 | + The number of registers provided at each level is four because it is believed that |
| 21 | + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for |
| 22 | + supervisor level, will be adequate for many years to come, perhaps for as long as |
| 23 | + the RISC-V ISA is in use. |
| 24 | + The exact number four is an attempted compromise between providing too few bits on |
| 25 | + the one hand and going overboard with CSRs that will never be used on the other. |
| 26 | + - id: csr-hstateen0-scope |
| 27 | + normative: true |
| 28 | + text: | |
| 29 | + The `stateen` registers at each level control access to state at all less-privileged |
| 30 | + levels, but not at its own level. |
| 31 | + - id: csr-hstateen0-effect |
| 32 | + normative: true |
| 33 | + text: | |
| 34 | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute |
| 35 | + in that privilege mode an instruction that implicitly updates the state without reading |
| 36 | + it may or may not raise an illegal instruction or virtual instruction exception. |
| 37 | + Such cases must be disambiguated by being explicitly specified one way or the other. |
| 38 | + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the |
| 39 | + ISA extensions that introduce the controlled state. |
| 40 | + - id: csr-hstateen0-encodings |
| 41 | + normative: true |
| 42 | + text: | |
| 43 | + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, |
| 44 | + except controlling accesses for a virtual machine (from VS and VU modes). |
| 45 | + - id: csr-hstateen0-zero |
| 46 | + normative: true |
| 47 | + text: | |
| 48 | + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), |
| 49 | + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. |
| 50 | + - id: csr-hstateen0-read-only |
| 51 | + normative: true |
| 52 | + text: | |
| 53 | + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one |
| 54 | + in the matching `mstateen` CSR. |
| 55 | +
|
| 56 | +definedBy: |
| 57 | + allOf: |
| 58 | + - H |
| 59 | + - Smstateen |
| 60 | + - Ssstateen |
| 61 | +fields: |
| 62 | + SE0: |
| 63 | + long_name: sstateen0 access control |
| 64 | + location: 63 |
| 65 | + description: | |
| 66 | + The SE0 bit in `hstateen0` controls access to the `sstateen0` CSR. |
| 67 | + type: RW |
| 68 | + reset_value: UNDEFINED_LEGAL |
| 69 | + sw_write(csr_value): | |
| 70 | + if (CSR[mstateen0].SE0 == 1'b0){ |
| 71 | + return 0; |
| 72 | + } |
| 73 | + return csr_value.SE0; |
| 74 | + ENVCFG: |
| 75 | + long_name: senvcfg access control |
| 76 | + location: 62 |
| 77 | + definedBy: |
| 78 | + name: S |
| 79 | + version: ">= 1.11" |
| 80 | + description: | |
| 81 | + The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs. |
| 82 | + type: RW |
| 83 | + reset_value: UNDEFINED_LEGAL |
| 84 | + sw_write(csr_value): | |
| 85 | + if (CSR[mstateen0].ENVCFG == 1'b0){ |
| 86 | + return 0; |
| 87 | + } |
| 88 | + return csr_value.ENVCFG; |
| 89 | + CSRIND: |
| 90 | + long_name: siselect and sireg* access control |
| 91 | + location: 60 |
| 92 | + definedBy: Sscsrind |
| 93 | + description: | |
| 94 | + The CSRIND bit in `hstateen0` controls access to the `siselect` and the |
| 95 | + `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind |
| 96 | + extensions. |
| 97 | + type: RW |
| 98 | + reset_value: UNDEFINED_LEGAL |
| 99 | + sw_write(csr_value): | |
| 100 | + if (CSR[mstateen0].CSRIND == 1'b0){ |
| 101 | + return 0; |
| 102 | + } |
| 103 | + return csr_value.CSRIND; |
| 104 | + AIA: |
| 105 | + long_name: Ssaia state access control |
| 106 | + location: 59 |
| 107 | + definedBy: Ssaia |
| 108 | + description: | |
| 109 | + The AIA bit in `hstateen0` controls access to all state introduced by |
| 110 | + the Ssaia extension and is not controlled by either the CSRIND or the |
| 111 | + IMSIC bits of `hstateen0`. |
| 112 | + type: RW |
| 113 | + reset_value: UNDEFINED_LEGAL |
| 114 | + sw_write(csr_value): | |
| 115 | + if (CSR[mstateen0].AIA == 1'b0){ |
| 116 | + return 0; |
| 117 | + } |
| 118 | + return csr_value.AIA; |
| 119 | + IMSIC: |
| 120 | + long_name: IMSIC state access control |
| 121 | + location: 58 |
| 122 | + definedBy: Ssaia |
| 123 | + description: | |
| 124 | + The IMSIC bit in `hstateen0` controls access to the guest IMSIC state, |
| 125 | + including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension. |
| 126 | +
|
| 127 | + Setting the IMSIC bit in `hstateen0` to zero prevents a virtual machine |
| 128 | + from accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0. |
| 129 | + type: RW |
| 130 | + reset_value: UNDEFINED_LEGAL |
| 131 | + sw_write(csr_value): | |
| 132 | + if (CSR[mstateen0].IMSIC == 1'b0){ |
| 133 | + return 0; |
| 134 | + } |
| 135 | + return csr_value.IMSIC; |
| 136 | + CONTEXT: |
| 137 | + long_name: scontext access control |
| 138 | + location: 57 |
| 139 | + definedBy: Sdtrig |
| 140 | + description: | |
| 141 | + The CONTEXT bit in `hstateen0` controls access to the `scontext` CSR provided |
| 142 | + by the Sdtrig extension. |
| 143 | + type: RW |
| 144 | + reset_value: UNDEFINED_LEGAL |
| 145 | + sw_write(csr_value): | |
| 146 | + if (CSR[mstateen0].CONTEXT == 1'b0){ |
| 147 | + return 0; |
| 148 | + } |
| 149 | + return csr_value.CONTEXT; |
| 150 | + CTR: |
| 151 | + long_name: ctr access control |
| 152 | + location: 54 |
| 153 | + description: | |
| 154 | + If the H extension is implemented and `mstateen0.CTR=1`, the `hstateen0.CTR` bit controls access to |
| 155 | + supervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` |
| 156 | + (really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0.CTR` is read-only 0 when |
| 157 | + `mstateen0.CTR=0`. |
| 158 | + type: RW |
| 159 | + reset_value: 0 |
| 160 | + sw_write(csr_value): | |
| 161 | + if (CSR[mstateen0].CTR == 1'b0){ |
| 162 | + return 0; |
| 163 | + } |
| 164 | + return csr_value.CTR; |
| 165 | + JVT: |
| 166 | + long_name: jvt access control |
| 167 | + location: 2 |
| 168 | + definedBy: Zcmt |
| 169 | + description: | |
| 170 | + The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. |
| 171 | + type: RW |
| 172 | + reset_value: UNDEFINED_LEGAL |
| 173 | + sw_write(csr_value): | |
| 174 | + if (CSR[mstateen0].JVT == 1'b0){ |
| 175 | + return 0; |
| 176 | + } |
| 177 | + return csr_value.JVT; |
| 178 | + FCSR: |
| 179 | + long_name: fcsr access control |
| 180 | + location: 1 |
| 181 | + #definedBy: |
| 182 | + #anyOf: [Zhinx, Zfinx, Zdinx] |
| 183 | + description: | |
| 184 | + The FCSR bit controls access to `fcsr` for the case when floating-point instructions |
| 185 | + operate on `x` registers instead of `f` registers as specified by the Zfinx and related |
| 186 | + extensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only |
| 187 | + zero (and hence read-only zero in `hstateen0` and `sstateen0` too). For convenience, |
| 188 | + when the `stateen` CSRs are implemented and `misa.F` = 0, then if the FCSR bit of a |
| 189 | + controlling `stateen0` CSR is zero, all floating-point instructions cause an illegal |
| 190 | + instruction trap (or virtual instruction trap, if relevant), as though they all access |
| 191 | + `fcsr`, regardless of whether they really do. |
| 192 | + type: RW |
| 193 | + reset_value: UNDEFINED_LEGAL |
| 194 | + sw_write(csr_value): | |
| 195 | + if (CSR[mstateen0].FCSR == 1'b0){ |
| 196 | + return 0; |
| 197 | + } |
| 198 | + return csr_value.FCSR; |
| 199 | + C: |
| 200 | + long_name: custom state access control |
| 201 | + location: 0 |
| 202 | + description: | |
| 203 | + The C bit controls access to any and all custom state. The C bit of these registers is |
| 204 | + not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, |
| 205 | + `hstateen0`, or `sstateen0`. |
| 206 | + type: RW |
| 207 | + reset_value: UNDEFINED_LEGAL |
| 208 | + sw_write(csr_value): | |
| 209 | + if (CSR[mstateen0].C == 1'b0){ |
| 210 | + return 0; |
| 211 | + } |
| 212 | + return csr_value.C; |
| 213 | +sw_read(): | |
| 214 | + # for every bit in an mstateen CSR that is zero, the same bit |
| 215 | + # appears as read-only zero in the matching hstateen CSR |
| 216 | +
|
| 217 | + Bits<64> mstateen0_mask = $bits(CSR[mstateen0]); |
| 218 | + Bits<64> hstateen0_value = $bits(CSR[hstateen0]) & mstateen0_mask; |
| 219 | + return hstateen0_value; |
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