fix(data): correct f* assembly operand names and more (#822)

- Correct operand and register names to be correct name/type
- Correct field names
- Add missing rounding mode in a places
- Similar changes in documentation and IDL
- Change `fctmod.w.d` to require `rtz` rounding mode be specified
  to match the spec
- Correct implementation of load and store conditionals
  (although some are still missing)

Author: ThinkOpenly

arch/inst/D/fadd.d.yaml

@@ -11,17 +11,17 @@ description:
       `fadd.d` is analogous to `fadd.s` and performs double-precision floating-point addition between
       `xs1` and `xs2` and writes the final result to `xd`.
 definedBy: D
-assembly: xd, xs1, xs2, rm
+assembly: fd, fs1, fs2, rm
 encoding:
   match: 0000001------------------1010011
   variables:
-    - name: rs2
+    - name: fs2
       location: 24-20
-    - name: rs1
+    - name: fs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: fd
       location: 11-7
 access:
   s: always

arch/inst/D/fclass.d.yaml

@@ -7,13 +7,13 @@ long_name: No synopsis available
 description: |
   No description available.
 definedBy: D
-assembly: xd, xs1
+assembly: xd, fs1
 encoding:
   match: 111000100000-----001-----1010011
   variables:
-    - name: rs1
+    - name: fs1
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always

arch/inst/D/fcvt.d.l.yaml

@@ -11,15 +11,15 @@ description:
       `fcvt.d.l` converts a 64-bit signed integer, in integer register `xs1` into a double-precision
       floating-point number in floating-point register `fd`.
 definedBy: D
-assembly: xd, xs1, rm
+assembly: fd, xs1, rm
 encoding:
   match: 110100100010-------------1010011
   variables:
-    - name: rs1
+    - name: xs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: fd
       location: 11-7
 access:
   s: always

arch/inst/D/fcvt.d.lu.yaml

@@ -11,15 +11,15 @@ description:
       `fcvt.d.lu` converts to or from a 64-bit unsigned integer, `xs1` into a double-precision
       floating-point number in floating-point register `fd`.
 definedBy: D
-assembly: xd, xs1, rm
+assembly: fd, xs1, rm
 encoding:
   match: 110100100011-------------1010011
   variables:
-    - name: rs1
+    - name: xs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: fd
       location: 11-7
 access:
   s: always

arch/inst/D/fcvt.d.s.yaml

@@ -13,15 +13,15 @@ description:
       encodes the datatype of the source, and the `fmt` field encodes the datatype of the destination.
       `fcvt.d.s` will never round.
 definedBy: D
-assembly: xd, xs1, rm
+assembly: fd, fs1, rm
 encoding:
   match: 010000100000-------------1010011
   variables:
-    - name: rs1
+    - name: fs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: fd
       location: 11-7
 access:
   s: always

arch/inst/D/fcvt.d.w.yaml

@@ -12,15 +12,15 @@ description:
       floating-point number in floating-point register `fd`.
       Note `fcvt.d.w` always produces an exact result and is unaffected by rounding mode.
 definedBy: D
-assembly: xd, xs1, rm
+assembly: fd, xs1, rm
 encoding:
   match: 110100100000-------------1010011
   variables:
-    - name: rs1
+    - name: xs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: fd
       location: 11-7
 access:
   s: always

arch/inst/D/fcvt.d.wu.yaml

@@ -12,15 +12,15 @@ description:
       floating-point number in floating-point register `fd`.
       Note `fcvt.d.wu` always produces an exact result and is unaffected by rounding mode.
 definedBy: D
-assembly: xd, xs1, rm
+assembly: fd, xs1, rm
 encoding:
   match: 110100100001-------------1010011
   variables:
-    - name: rs1
+    - name: xs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: fd
       location: 11-7
 access:
   s: always

arch/inst/D/fcvt.l.d.yaml

@@ -11,15 +11,15 @@ description:
       `fcvt.l.d` converts a double-precision floating-point number in floating-point register `fs1`
       to a signed 64-bit integer, in integer register `xd`.
 definedBy: D
-assembly: xd, xs1, rm
+assembly: xd, fs1, rm
 encoding:
   match: 110000100010-------------1010011
   variables:
-    - name: rs1
+    - name: fs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always

arch/inst/D/fcvt.lu.d.yaml

@@ -11,15 +11,15 @@ description:
       `fcvt.lu.d` converts a double-precision floating-point number in floating-point register `xs1`
       to an unsigned 64-bit integer, in integer register `xd`.
 definedBy: D
-assembly: xd, xs1, rm
+assembly: xd, fs1, rm
 encoding:
   match: 110000100011-------------1010011
   variables:
-    - name: rs1
+    - name: fs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always

arch/inst/D/fcvt.s.d.yaml

@@ -13,15 +13,15 @@ description:
        registers. The `rs2` field encodes the datatype of the source, and the `fmt` field encodes the datatype
        of the destination. `fcvt.s.d` rounds according to the RM field
 definedBy: D
-assembly: xd, xs1, rm
+assembly: fd, fs1, rm
 encoding:
   match: 010000000001-------------1010011
   variables:
-    - name: rs1
+    - name: fs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: fd
       location: 11-7
 access:
   s: always