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Add spec to FP Computational and Conversion Instructions (#810)
This PR adds missing long_name and description to some FP Computational and remaining FP Conversion Instructions.
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‎arch/inst/D/fadd.d.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fadd.d
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Add Double-precision
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description:
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- id: inst-fadd.d-behaviour
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normative: false
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text: |
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`fadd.d` is analogous to `fadd.s` and performs double-precision floating-point addition between
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`xs1` and `xs2` and writes the final result to `xd`.
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definedBy: D
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assembly: xd, xs1, xs2, rm
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encoding:

‎arch/inst/D/fcvt.d.l.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.d.l
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Long to Double-precision
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description:
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- id: inst-fcvt.d.l-behaviour
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normative: false
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text: |
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`fcvt.d.l` converts a 64-bit signed integer, in integer register `xs1` into a double-precision
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floating-point number in floating-point register `fd`.
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

‎arch/inst/D/fcvt.d.lu.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.d.lu
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Unsigned Long to Double-precision
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description:
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- id: inst-fcvt.d.lu-behaviour
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normative: false
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text: |
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`fcvt.d.lu` converts to or from a 64-bit unsigned integer, `xs1` into a double-precision
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floating-point number in floating-point register `fd`.
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

‎arch/inst/D/fcvt.d.s.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.d.s
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Single-precision to Double-precision
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description:
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- id: inst-fcvt.d.s-behaviour
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normative: false
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text: |
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The single-precision to double-precision conversion instruction, `fcvt.d.s` is encoded in the OP-FP
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major opcode space and both the source and destination are floating-point registers. The `xs2` field
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encodes the datatype of the source, and the `fmt` field encodes the datatype of the destination.
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`fcvt.d.s` will never round.
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

‎arch/inst/D/fcvt.d.w.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.d.w
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Word to Double-precision
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description:
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- id: inst-fcvt.d.w-behaviour
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normative: false
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text: |
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`fcvt.d.w` converts a 32-bit signed integer, in integer register `xs1` into a double-precision
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floating-point number in floating-point register `fd`.
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Note `fcvt.d.w` always produces an exact result and is unaffected by rounding mode.
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

‎arch/inst/D/fcvt.d.wu.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.d.wu
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Unsigned Word to Double-precision
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description:
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- id: inst-fcvt.d.wu-behaviour
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normative: false
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text: |
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`fcvt.d.wu` converts a 32-bit unsigned integer in integer register `fs1` into a double-precision
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floating-point number in floating-point register `fd`.
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Note `fcvt.d.wu` always produces an exact result and is unaffected by rounding mode.
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

‎arch/inst/D/fcvt.l.d.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.l.d
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Double-precision to Long
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description:
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- id: inst-fcvt.l.d-behaviour
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normative: false
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text: |
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`fcvt.l.d` converts a double-precision floating-point number in floating-point register `fs1`
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to a signed 64-bit integer, in integer register `xd`.
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

‎arch/inst/D/fcvt.lu.d.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.lu.d
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Double-precision to Unsigned Long
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description:
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- id: inst-fcvt.lu.d-behaviour
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normative: false
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text: |
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`fcvt.lu.d` converts a double-precision floating-point number in floating-point register `xs1`
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to an unsigned 64-bit integer, in integer register `xd`.
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

‎arch/inst/D/fcvt.s.d.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.s.d
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Double-precision to Single-precision
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description:
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- id: inst-fcvt.s.d-behaviour
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normative: false
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text: |
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`fcvt.s.d` converts a double-precision floating-point number to a single-precision floating-point number.
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This is encoded in the OP-FP major opcode space and both the source and destination are floating-point
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registers. The `rs2` field encodes the datatype of the source, and the `fmt` field encodes the datatype
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of the destination. `fcvt.s.d` rounds according to the RM field
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

‎arch/inst/D/fcvt.w.d.yaml

Lines changed: 7 additions & 3 deletions
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$schema: inst_schema.json#
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kind: instruction
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name: fcvt.w.d
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long_name: No synopsis available
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description: |
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No description available.
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long_name: Floating-point Convert Double-precision to Word
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description:
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- id: inst-fcvt.w.d-behaviour
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normative: false
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text: |
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`fcvt.w.d` converts a double-precision floating-point number in floating-point register `xs1` to a
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signed 32-bit integer, in integer register `xd`.
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definedBy: D
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assembly: xd, xs1, rm
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encoding:

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